MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1556

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Performance Monitor
24.1.1
Figure 24-1
register (PMGC0), one 64-bit counter (PMC0), nine 32-bit counters, and two control registers per counter
(20 total control registers). The global control register PMGC0 affects all counters and takes priority over
local control registers. The local control registers are divided into two groups, as follows:
Performance monitor events are signalled by the functional blocks in the integrated device and are
selectively recorded in the PMCs. Sixty-four of these events are referred to as reference events, which can
be counted on any of the nine 32-bit counters. Counter-specific events can be counted only on the counter
where the event is defined.
The performance monitor can generate an interrupt on overflow. Several control registers specify how a
performance monitor interrupt is signalled. The PMCs can also be programmed to freeze when an interrupt
is signalled.
24-2
•
•
Local control A registers control counter freezing, overflow condition enable, event selection, and
burstiness. Local control register PMLCA0, which controls counter PMC0, does not contain event
selection because PMC0 counts only cycles.
Local control B registers control the start and stop triggering, contain the counters’ threshold
values, and the value of the threshold multiplier. Local control register PMLCB0, which controls
PMC0, does not contain threshold information because PMC0 only counts cycles.
Overview
is a high-level block diagram of the performance monitor, which consists of a global control
Event 0
Event 1
Event 2
Event 3
Event 4
Event 9
...
Event Signals
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 24-1. Performance Monitor Block Diagram
PMC0 (upper)
PMLCA9
PMLCA0
PMLCA1
PMLCA2
PMLCA3
Counters and Registers
PMC1
PMC2
PMC3
...
PMC9
Global Control Register
Local Control Registers
Performance Monitor
...
Control Logic
Counters
PMGC0
PMC0 (lower)
32-bit
PMLCB0
PMLCB1
PMLCB2
PMLCB3
PMLCB9
...
Output Signals
Freescale Semiconductor
Interrupt ( int )
Read Data