MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 306

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
Table 8-18
above.
8-32
10–11 CKE_CNTL Clock enable control. Allows software to globally clear or set all CKE signals issued to DRAM. Once
13–15
16–31 MD_VALUE Mode register value. This field, which specifies the value that is presented on the memory address pins of
Bits
12
MD_VALUE
CKE_CNTL
SET_REF
SET_PRE
MD_SEL
CS_SEL
MD_EN
Field
WRCW
Name
—
shows how DDR_SDRAM_MD_CNTL fields should be set for each of the tasks described
software has forced the value driven on CKE, that value continues to be forced until software clears the
CKE_CNTL bits. At that time, the DDR controller continues to drive the CKE signals to the same value
forced by software until another event causes the CKE signals to change (such as, self refresh entry/exit,
power down entry/exit).
00 CKE signals are not forced by software.
01 CKE signals are forced to a low value by software.
10 CKE signals are forced to a high value by software.
11 Reserved
Write register control word. If software sets this bit, then a register control word is written by asserting the
selected chip selects while providing the programmed data on the MA and MBA signals. The RAS, CAS,
and WE will remain deasserted during this write The MD_EN field should also be set to force a register
control word write. This should only be set if DDR3 registered DIMM s are used, and the register needs to
be configured. If DDR_SDRAM_MD_CNTL is used to write RCW2 specifically, then software must
guarantee that the timing parameter, t-STAB , is met before future accesses to the controller are allowed. In
addition, DDR_SDRAM_MD_CNTL register cannot be used to write the RCWs if write leveling is used,
since write leveling is run automatically before DDR_SDRAM_MD_CNTL can be used to force RCW
writes..
0 Indicates that a register control word write will not be issued if MD_EN is set.
1 Indicates that a register control word write is issued if MD_EN is set.
Reserved
the DDR controller during a mode register set command, is significant only when this register is used to
issue a mode register set command or a precharge or precharge all command.
For a mode register set command, this field contains the data to be written to the selected mode register.
For a precharge command, only bit five is significant:
0 Issue a precharge command; MD_SEL selects the logical bank to be precharged
1 Issue a precharge all command; all logical banks are precharged
Select mode register.
See
Value written to mode
register
Mode Register Set
Table 8-17. DDR_SDRAM_MD_CNTL Field Descriptions (continued)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 8-17
Table 8-18. Settings of DDR_SDRAM_MD_CNTL Fields
1
0
0
0
.
Chooses chip select (CS)
Refresh
—
—
0
1
0
0
Description
Only bit five is significant.
See
Selects logical bank
Table 8-17
Precharge
0
0
1
0
.
See
Clock Enable Signals
Table 8-17
Freescale Semiconductor
Control
—
—
—
—
—
—
.