MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1367

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.3.2.20 Endpoint Complete Register (ENDPTCOMPLETE)—Non-EHCI
This register is not defined in the EHCI specification. This register is only used in device mode.
21.3.2.21 Endpoint Control Register 0 (ENDPTCTRL0)—Non-EHCI
This register is not defined in the EHCI specification. Every device will implement endpoint 0 as a control
endpoint.
Freescale Semiconductor
Offset 0x1BC
Reset
31–22
21–16 ETCE Endpoint transmit complete event. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software
15–6
Bits
15–6
5–0
Bits
5–0
W
R
31
Name
ERCE Endpoint receive complete event. Each bit indicates a received event (OUT/SETUP) occurred and software
ERBR Endpoint receive buffer ready. One bit for each endpoint indicates status of the respective endpoint buffer. This
Name
—
—
—
Reserved, should be cleared
should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit
is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one will clear
the corresponding bit in this register. ETCE[5] (bit 21 of the register) corresponds to endpoint 5.
Reserved, should be cleared
should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is
set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one will clear
the corresponding bit in this register. ERCE[5] corresponds to endpoint 5.
Reserved, should be cleared
bit is set by the hardware as a response to receiving a command from a corresponding bit in the
ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and
endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits
set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through
the ENDPTFLUSH register. ERBR[5] corresponds to endpoint 5.
Note that these bits will be momentarily cleared by hardware during hardware endpoint re-priming operations
when a dTD is retired, and the dQH is updated.
Table 21-27. ENDPTSTATUS Register Field Descriptions (continued)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
Table 21-28. ENDPTCOMPLETE Register Field Descriptions
Figure 21-26. Endpoint Complete (ENDPTCOMPLETE)
22 21
ETCE
w1c
All zeros
Description
16 15
Description
—
Universal Serial Bus Interfaces
6
5
Access: w1c
ERCE
w1c
21-33
0