MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 709

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.4.3.2.4
Data read instructions assert LFRE repeatedly to transfer one or more bytes of read data from the NAND
Flash EEPROM. Data read instructions are distinguished by their data destination:
13.4.3.2.5
Data write instructions assert LFWE repeatedly (with LFCLE and LFALE both negated) to transfer one or
more bytes of write data to the NAND Flash EEPROM. Data write instructions are distinguished by their
data source:
Freescale Semiconductor
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User-defined address—UA. This instruction allows the FCM to write a user-defined address byte,
which is read from the next AS field in MDR, starting at MDR[AS0]. Each subsequent UA
instruction reads an adjacent AS field in MDR, until all four AS bytes (MDR[AS0], MDR[AS1],
MDR[AS2], MDR[AS3]) have been sent; a fifth and any following UA instructions send zero as
the address byte. Note that each UA instruction advances the MDR pointer for writes by one byte,
and therefore a mix of UA and WS instructions can consume adjacent bytes from MDR.
Read data to buffer RAM immediately—RB. This instruction reads FBCR[BC] bytes of data into
the current FCM RAM buffer addressed by FPAR. If FBCR[BC] = 0, an entire page (including
spare region) is transferred in a burst, starting at the page boundary, and the ECC calculation is
checked against the ECC stored in the spare region. Correctable ECC errors are corrected and
reported in LTECCR[SBCE]; other errors may cause an interrupt if enabled. If the value of
FBCR[BC] takes the read pointer beyond the end of the spare region in the buffer, FCM discards
any excess bytes read.
Read data/status to MDR immediately—RS. This instruction asserts LFRE exactly once to read
one byte (8-bit port size) of data into the next AS field of MDR. Reads beyond the fourth byte of
MDR are discarded. The MDR read pointer is independent of the MDR write pointer used by UA
and WS instructions.
Read data to buffer RAM once waited on ready—RBW. This instruction first polls the LFRB pin,
waiting for it to go high, before proceeding with a read to buffer as described for the RB instruction.
Sampling and time-outs for polling the LFRB pin follow the behavior of CWn instructions.
Read data/status to MDR once waited on ready—RSW. This instruction first polls the LFRB pin,
waiting for it to go high, before proceeding with a status read to MDR as described for the RS
instruction. Sampling and time-outs for polling the LFRB pin follow the behavior of CWn
instructions.
Write data from FCM buffer RAM—WB. This instruction writes FBCR[BC] bytes of data from
the current FCM RAM buffer addressed by FPAR. If FBCR[BC] = 0, an entire page (including
spare region) is transferred in a burst, starting at the page boundary, and the ECC calculation is
stored in the appropriate FECCn registers and spare region in accordance with the setting of
FMR[ECCM]. If the value of FBCR[BC] takes the write pointer beyond the end of the spare region
in the buffer, the value of data written by FCM is undefined.
Write data/status from MDR—WS. This instruction asserts LFWE exactly once to write one byte
(8-bit port size) of data taken from the next AS field of MDR. Attempts to write beyond four bytes
of MDR has the effect of writing zeros. The MDR write pointer is independent of the MDR read
pointer used by RS and RSW instructions.
FCM Data Read Instructions
FCM Data Write Instructions
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Enhanced Local Bus Controller
13-67