MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 659

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 13-8
Freescale Semiconductor
17–18
0–16
Bits
19
20
21
22
23
BCTLD
Name
CSCT
PGS
CST
AM
—
—
describes ORn fields for FCM mode.
FCM address mask. Masks corresponding BR n bits. Masking address bits independently allows external
devices of different size address ranges to be used. Address mask bits can be set or cleared in any order
in the field, allowing a resource to reside in more than one area of the address map.
0 Corresponding address bits are masked.
1 Corresponding address bits are used in the comparison between base and transaction addresses.
Reserved
Buffer control disable. Disables assertion of LBCTL during access to the current memory bank.
0 LBCTL is asserted upon access to the current memory bank.
1 LBCTL is not asserted upon access to the current memory bank.
Reserved
NAND Flash EEPROM page size, buffer size, and block size.
0 Page size of 512 main area bytes plus 16 spare area bytes (small page devices);
1 Page size of 2048 main area bytes plus 64 spare area bytes (large page devices);
Chip select to command time. Determines how far in advance LCS n is asserted prior to any bus activity
during a NAND Flash access handled by the FCM. This helps meet chip-select setup times for slow
memories.
Command setup time. Determines the delay of LFWE assertion relative to the command, address, or data
change when the external memory access is handled by the FCM.
FCM RAM buffers are 1 Kbyte each; Flash block size of 16 Kbytes.
FCM RAM buffers are 4 Kbytes each; Flash block size of 128 Kbytes.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
TRLX
TRLX
0
0
1
1
0
0
1
1
CSCT
CST
0
1
0
1
0
1
0
1
Table 13-8. OR n
The chip-select is asserted 1 clock cycle before any command.
The chip-select is asserted 4 clock cycles before any command.
The chip-select is asserted 2 clock cycles before any command.
The chip-select is asserted 8 clock cycles before any command.
The write-enable is asserted coincident with any command.
The write-enable is asserted 0.25 clock cycles after any command, address, or
data.
The write-enable is asserted 0.5 clock cycles after any command, address, or
data.
The write-enable is asserted 1 clock cycle after any command, address, or data.
—
FCM Field Descriptions
Description
Meaning
Meaning
Enhanced Local Bus Controller
13-17