MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 804

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.5.3.3.2
The eTSEC writes to this register under the following conditions:
14-56
24–25
Bits
26
27
28
29
30
31
•
•
•
A frame interrupt event occurred on one or more RxBD rings
The receiver runs out of descriptors due to a busy condition on a RxBD ring
The receiver was halted because an error condition was encountered while receiving a frame
PRSDEP Parser control. The level of parser layer recognition is determined as follows:
BC_REJ
PRSFM
PROM
EMEN
Name
RSF
—
Receive Status Register (RSTAT)
00 Parser disabled. Receive frame filer must also be disabled by clearing RCTRL[FILREN]. This should
01 Only L2 (Ethernet) protocols are recognized. For packets received over a FIFO interface, this parse
10 L2 and L3 (IP) protocols are recognized over any interface not configured as a FIFO interface. If
11 L2, L3, and L4 (TCP/UDP) protocols are recognized over any interface not configured as a FIFO
If this field is non-zero, a TOE frame control block is prepended to the received frame, and the first RxBD
points to the FCB.
Note that if PRSDEP is cleared, VLEX must be cleared as well. (VLAN tag extraction is only supported
when the parser is enabled.) Also, if PRSDEP is cleared, FILREN must also be cleared.
FIFO-mode parsing
0 L2 parsing in FIFO mode is not available. Must be 0 for non-FIFO modes.
1 L2 parsing in FIFO mode is available
Broadcast frame reject. If this bit is set, frames with DA (destination address) = FFFF_FFFF_FFFF are
rejected unless RCTRL[PROM] is set. If both BC_REJ and RCTRL[PROM] are set, then frames with
broadcast DA are accepted and the M (MISS) bit is set in the receive BD.
Promiscuous mode. All Ethernet frames, regardless of destination address, are accepted.
Receive short frame mode. When set, enables the reception of frames shorter than 64 bytes. For packets
received over the FIFO packet interface, this bit has no effect (packets shorter than 64 bytes are always
accepted).
0 Ethernet frames less than 64B in length are silently dropped.
1) Frames more than 16B and less than 64B in length are accepted upon a DA match.
Note that frames less than or equal to 16B in length are always silently dropped.
Exact match MAC address enable. If this bit is set, the MAC01ADDR1–MAC15ADDR1 and
MAC01ADDR2–MAC15ADDR2 registers are recognized as containing MAC addresses aliasing the
MAC’s station address. Setting this bit therefore allows eTSEC to receive Ethernet frames having a
destination address matching one of these 15 addresses.
Reserved
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
interface. If RCTRL[PRSFM]=0, this encoding means L3 and L4 (TCP/UDP) protocols are recognized
for packets received over a FIFO interface. If RCTRL[PRSDEP]=1, this encoding means L2, L3, and
L4 (TCP/UDP) protocols are recognized for packets received over a FIFO interface.
be the setting for raw (non-IP) packets received over a FIFO interface.
level is available only if RCTRL[PRSFM]=1.
RCTRL[PRSFM]=0, this encoding means L3 (IP) only protocols are recognized for packets received
over a FIFO interface. If RCTRL[PRSFM]=1, this encoding means L2 and L3 (IP) protocols are
recognised for packets received over a FIFO interface.
Table 14-29. RCTRL Field Descriptions (continued)
Description
Freescale Semiconductor