MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1641

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
2
3
Freescale Semiconductor
0x2_4E50–
0x2_6000–
0x2_4EAC TMR_ETTS2_L* - Time stamp of general purpose external trigger
0x2_4E0C TMR_PEVENT* - time stamp event register
0x2_4E1C TMR_CNT_L* - timer counter low register
0x2_4E2C Reserved
0x2_4E4C TMR_ALARM2_L* - Timer alarm 2 high register
0x2_4E7C
0x2_4EA0 TMR_ETTS1_H* - Time stamp of general purpose external
0x2_4EA4 TMR_ETTS1_L* - Time stamp of general purpose external trigger
0x2_4EA8 TMR_ETTS2_H* - Time stamp of general purpose external
0x2_4EB0
0x2_4FFF
0x2_6FFF
0x2_4E08 TMR_TEMASK* - Timer event mask register
0x2_4E10 TMR_PEMASK* - Timer event mask register
0x2_4E14 TMR_STAT* - time stamp status register
0x2_4E18 TMR_CNT_H* - timer counter high register
0x2_4E20 TMR_ADD* - Timer drift compensation addend register
0x2_4E24 TMR_ACC* - Timer accumulator register
0x2_4E28 TMR_PRSC* -Timer prescale
0x2_4E30 TMROFF_H* - Timer offset high
0x2_4E34 TMROFF_L* - Timer offset low
0x2_4E40 TMR_ALARM1_H* - Timer alarm 1 high register
0x2_4E44 TMR_ALARM1_L* - Timer alarm 1 high register
0x2_4E48 TMR_ALARM2_H* - Timer alarm 2 high register
0x2_4E80 TMR_FIPER1* - Timer fixed period interval
0x2_4E84 TMR_FIPER2* - Timer fixed period interval
0x2_4E88 TMR_FIPER*3 - Timer fixed period interval
eTSEC1
Registers denoted * are new to the enhanced TSEC and not supported by PowerQUICC III TSECs.
Key: R = read only, WO = write only, R/W = read and write, LH = latches high, SC = self-clearing.
Cleared on read.
Offset
–
Reserved
trigger
trigger
Reserved
eTSEC3 REGISTERS
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
4
Table A-2. Module Memory Map (continued)
Name
1
Other eTSECs
Complete List of Configuration, Control, and Status Registers
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
2
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0002
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
—
—
—
14.5.3.11.10/14-130
14.5.3.11.11/14-131
14.5.3.11.11/14-131
14.5.3.11.12/14-131
14.5.3.11.13/14-132
14.5.3.11.14/14-133
14.5.3.11.3/14-125
14.5.3.11.4/14-126
14.5.3.11.5/14-127
14.5.3.11.6/14-128
14.5.3.11.7/14-128
14.5.3.11.7/14-128
14.5.3.11.8/14-129
14.5.3.11.9/14-130
Section/Page
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A-29