MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1381

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.5.4
All full-speed isochronous transfers through the internal transaction translator are managed using the siTD
data structure. This data structure satisfies the operational requirements for managing the split transaction
protocol.
Freescale Semiconductor
31–12
31–12
31–12
10–0
11–2
11–2
Bits
Bits
Bits
1–0
6–0
11
7
Buffer Pointer
Buffer Pointer
Buffer Pointer
Packet Size
Maximum
(Page 1)
Device Address
(Page 2)
Name
Split Transaction Isochronous Transfer Descriptor (siTD)
Name
Name
I/O
Mult
—
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
This is a 4K aligned pointer to physical memory. Corresponds to memory address bits 31–12.
Direction (I/O). This field encodes whether the high-speed transaction should use an IN or OUT PID.
0 OUT
1 IN
This directly corresponds to the maximum packet size of the associated endpoint ( wMaxPacketSize ).
This field is used for high-bandwidth endpoints where more than one transaction is issued per
transaction description (for example, per micro-frame). This field is used with the Multi field to support
high-bandwidth pipes. This field is also used for all IN transfers to detect packet babble. Software
should not set a value larger than 1024 (0x400). Any value larger yields undefined results.
This is a 4K-aligned pointer to physical memory. Corresponds to memory address bits 31–12.
Reserved, should be cleared. This bit reserved for future use and should be cleared.
Indicates to the host controller the number of transactions that should be executed per transaction
description (for example, per micro-frame).
00 Reserved, should be cleared. A zero in this field yields undefined results.
01 One transaction to be issued for this endpoint per micro-frame
10 Two transactions to be issued for this endpoint per micro-frame
11 Three transactions to be issued for this endpoint per micro-frame
This is a 4K aligned pointer to physical memory. Corresponds to memory address bits 31–12.
Reserved, should be cleared. These bits reserved for future use and should be cleared.
Table 21-40. Buffer Pointer Page 0 (Plus) (continued)
Reserved, should be cleared. Reserved for future use and should be initialized by software
to zero.
This field selects the specific device serving as the data source or sink.
Table 21-41. iTD Buffer Pointer Page 1 (Plus)
Table 21-42. Buffer Pointer Page 2 (Plus)
Table 21-43. Buffer Pointer Page 3–6
Description
Description
Description
Universal Serial Bus Interfaces
21-47