MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 942

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.6.7
There is a push in industrial control applications to use Ethernet as the principal link layer for
communications. This requires Ethernet to be used for both data transfer and real-time control. For
real-time systems, each node is required to be synchronized to a master clock. The precision of this clock
is dictated by the application, but generally needs to be of the order of <1uSec for high-speed machinery
(for example, printing presses).
IEEE 1588 [1588] specifies a mechanism for synchronizing multiple nodes to a master clock. Support for
1588 can be done entirely in software running on a host CPU, but applications that require sub 10uSec
accuracy will need hardware support for accurate timestamping of incoming packets.
The eTSEC includes a new timer clock module to support the IEEE Std. 1588 timer standard. The
following sections describe the features, programming model, and implementation information.
14.6.7.1
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64-bit free running timer running from an external oscillator or internal clock
Programmable timer oscillator clock selection
Self-correcting precision timer with nano-second resolution
Time stamp all incoming packets inline
— Maskable interrupts on received PTP packet’s filer rule match
Time stamp transmit packets when instructed in the TxFCB
— Maskable interrupts on transmit timestamp capture
Two Tx time stamp registers per eTSEC with 16-bit tag for each of them to support burst mode.
Time stamp capture on two general-purpose external triggers
— Maskable interrupts on GPIO timestamp trigger
— Programmable polarity of external trigger (GPIO) edge
Two 64-bit alarm (future time) registers for future time comparison
— Maskable interrupts on alarm
Three programmable timer output pulse period phase aligned with 1588 timer clock
— Maskable interrupts associated with each pulse
Separate maskable timer interrupt event register
Recognition of incoming PTP packet through filer rule match
Phase aligned adjustable (divide by N) clock output
Supports all Ethernet modes supported by the eTSEC, including full- and half-duplex modes
Supports both master and slave modes
Supports timestamp of nano-second resolution
Hardware Assist for IEEE Std. 1588-CompatibleTimestamping
Features
IEEE 1588 timestamping is not supported in conjunction with the SGMII
10/100 interface mode.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
NOTE
Freescale Semiconductor