MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1240

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller
19-10
28–24
23–19
17–16
15–14
7–6
Bit
29
18
13
12
11
10
9
8
5
4
3
2
SNTFU
Name
SIGU
DOE
DUE
CER
FOR
CET
FOT
ME
PR
BE
FE
—
—
—
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
BIST error. When the protocol is placed into BIST this bit maps the BIST error.
0 Indicates the link layer is passing BIST
1 Indicates that the link layer is not passing BIST
When the protocol is not in BIST this bit will assert high and can be ignored.
Reserved
Reserved
SATA controller master error. Indicates if the host received an error on the system bus interface
during the access to memory.
0 No error response is received when a transfer was made into the memory
1 Error response is received during the transfer into the memory
Reserved
Reserved
Data underrun.
0 No underrun encountered (data was retrieved from external memory in time to send a complete
1 The SATA controller encountered an underrun condition while sending the FIS
Data overrun.
0 No overrun condition encountered
1 The SATA controller encountered an overrun condition while receiving the FIS
CRC error Tx. When set, this bit indicates that one or more CRC errors occurred in Tx data path.
CRC error Rx. When set, this bit indicates that one or more CRC errors occurred in Rx data path.
FIFO overflow Tx. When set, this bit indicates that Tx FIFO is in overflow condition while sending
FIS.
FIFO overflow Rx. When set, this bit indicates that Rx FIFO is in overflow condition while receiving
FIS.
Reserved
Fatal error. When set, this bit indicates that fatal error occurred in SATA controller. In this state, the
interrupt will be generated if FATAL_INT is set in the host control register. Write ‘1’ to clear the
interrupt source.
PHY ready. When set, this bit indicates that PHY READY signal was changed. In this state, the
interrupt will be generated if PHYRDY_INT is set in the host control register. Write ‘1’ to clear the
interrupt source.
Signature update. When set, this bit indicates that the signature is updated in the host signature
register. In this state, the interrupt will be generated if SIG_INT is set in the host control register.
Write ‘1’ to clear the interrupt source.
SNotification update. When set, this bit indicates that the SNotification register has at least one bit
set. In this state, the interrupt will be generated if SNTFY_INT is set in the host control register.
Write ‘1’ to clear the interrupt source.
FIS)
Table 19-8. HStatus Field Descriptions (continued)
Description
Freescale Semiconductor