MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet

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MPC8313E PowerQUICC™ II Pro Family Reference Manual Integrated Processor Supports MPC8313E MPC8313 MPC8313ERM Rev. 2 12/2008 ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...

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... High-End Printer I/O Processor................................................................................. 1-20 1.3.3 IEEE Std. 1588 in Test and Measurement and Industrial Automation ...................... 1-21 1.3.4 IEEE Std. 802.11n WLAN Access Point ................................................................... 1-23 1.3.5 Media Server.............................................................................................................. 1-24 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Contents Title Contents About This Book Chapter 1 Overview Page ...

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... PCI Host/Agent Configuration .......................................................................... 4-16 4.3.2.2.2 Boot Memory Space (BMS) .............................................................................. 4-17 4.3.2.2.3 Boot Sequencer Configuration .......................................................................... 4-17 4.3.2.2.4 Boot ROM Location .......................................................................................... 4-18 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev Contents Title Chapter 2 Memory Map Chapter 3 Signal Descriptions Chapter 4 Reset, Clocking, and Initialization Page Number Freescale Semiconductor ...

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... System PLL Mode Register (SPMR) .................................................................... 4-37 4.5.2.2 Output Clock Control Register (OCCR)................................................................ 4-39 4.5.2.3 System Clock Control Register (SCCR)................................................................ 4-40 5.1 Introduction...................................................................................................................... 5-1 5.2 Local Memory Map Overview and Example .................................................................. 5-1 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Contents Title Chapter 5 System Configuration Page Number v ...

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... System Configuration Register Memory Map........................................................... 5-16 5.3.2 System Configuration Registers ................................................................................ 5-17 5.3.2.1 System General Purpose Register Low (SGPRL) ................................................. 5-17 5.3.2.2 System General Purpose Register High (SGPRH) ................................................ 5-17 5.3.2.3 System Part and Revision ID Register (SPRIDR) ................................................. 5-18 5.3.2.3.1 SPRIDR[PARTID] Coding ................................................................................ 5-18 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev Contents Title Page Number Freescale Semiconductor ...

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... Real Time Counter Alarm Register (RTALR) ....................................................... 5-40 5.5.6 Functional Description............................................................................................... 5-41 5.5.6.1 Real Time Counter Unit......................................................................................... 5-41 5.5.6.2 RTC Operational Modes ........................................................................................ 5-41 5.5.7 RTC Programming Guidelines................................................................................... 5-42 5.6 Periodic Interval Timer (PIT) ........................................................................................ 5-42 5.6.1 PIT Overview............................................................................................................. 5-42 5.6.2 PIT Features............................................................................................................... 5-43 5.6.3 PIT Modes of Operation ............................................................................................ 5-43 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Contents Title Page Number vii ...

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... GTM Registers................................................................................................... 5-64 5.8 Power Management Control (PMC) .............................................................................. 5-64 5.8.1 External Signal Description ....................................................................................... 5-65 5.8.2 PMC Memory Map/Register Definition .................................................................... 5-65 5.8.2.1 Power Management Controller Configuration Register (PMCCR)....................... 5-66 5.8.2.2 Power Management Controller Event Register (PMCER).................................... 5-67 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 viii Contents Title Page Number Freescale Semiconductor ...

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... Arbiter Event Response Register (AERR)................................................................. 6-10 6.3 Functional Description................................................................................................... 6-10 6.3.1 Arbitration Policy ...................................................................................................... 6-10 6.3.1.1 Address Bus Arbitration with PRIORITY[0:1] ..................................................... 6-11 6.3.1.2 Address Bus Arbitration with REPEAT ................................................................ 6-12 6.3.1.3 Address Bus Arbitration after ARTRY.................................................................. 6-13 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Contents Title Chapter 6 Arbiter and Bus Monitor Page Number ix ...

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... JTAG Test and Debug Interface............................................................................. 7-12 7.1.7.4 Clock Multiplier.................................................................................................... 7-12 7.1.7.5 Core Performance Monitor .................................................................................... 7-12 7.2 PowerPC Architecture Implementation ......................................................................... 7-13 7.3 Implementation-Specific Information............................................................................ 7-13 7.3.1 Register Model........................................................................................................... 7-14 7.3.1.1 UISA Registers ...................................................................................................... 7-16 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev Contents Title Chapter 7 e300 Processor Core Overview Page Number Freescale Semiconductor ...

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... Breakpoint Signaling ............................................................................................. 7-38 7.4 Differences Between Cores........................................................................................... 7-39 Integrated Programmable Interrupt Controller (IPIC) 8.1 Introduction...................................................................................................................... 8-1 8.2 Features ............................................................................................................................ 8-4 8.3 Modes of Operation ......................................................................................................... 8-4 8.3.1 Core Enable Mode ....................................................................................................... 8-4 8.3.2 Core Disable Mode ...................................................................................................... 8-5 8.4 External Signal Description ............................................................................................. 8-5 8.4.1 Overview...................................................................................................................... 8-5 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Contents Title Chapter 8 Page Number xi ...

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... Masking Interrupt Sources......................................................................................... 8-34 8.6.8 Interrupt Vector Generation and Calculation ............................................................. 8-35 8.6.9 Machine Check Interrupts.......................................................................................... 8-35 9.1 Introduction...................................................................................................................... 9-1 9.2 Features ............................................................................................................................ 9-2 9.2.1 Modes of Operation ..................................................................................................... 9-3 9.3 External Signal Descriptions ........................................................................................... 9-3 9.3.1 Signals Overview......................................................................................................... 9-3 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xii Contents Title Chapter 9 DDR Memory Controller Page Number Freescale Semiconductor ...

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... DDR SDRAM Refresh .............................................................................................. 9-44 9.5.8.1 DDR SDRAM Refresh Timing.............................................................................. 9-45 9.5.8.2 DDR SDRAM Refresh and Power-Saving Modes ................................................ 9-45 9.5.8.2.1 Self-Refresh in Sleep Mode............................................................................... 9-47 9.5.9 DDR Data Beat Ordering........................................................................................... 9-48 9.5.10 Page Mode and Logical Bank Retention ................................................................... 9-48 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Contents Title Page Number xiii ...

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... Flash Mode Register (FMR)................................................................................ 10-34 10.3.1.18 Flash Instruction Register (FIR) .......................................................................... 10-35 10.3.1.19 Flash Command Register (FCR) ......................................................................... 10-36 10.3.1.20 Flash Block Address Register (FBAR)................................................................ 10-37 10.3.1.21 Flash Page Address Register (FPAR) .................................................................. 10-37 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xiv Contents Title Chapter 10 Enhanced Local Bus Controller Page Number Freescale Semiconductor ...

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... FCM Read Data Timing .................................................................................. 10-68 10.4.3.3.5 FCM Extended Read Hold Timing.................................................................. 10-69 10.4.3.4 FCM Boot Chip-Select Operation ....................................................................... 10-69 10.4.3.4.1 FCM Bank 0 Reset Initialization ..................................................................... 10-70 10.4.3.4.2 Boot Block Loading into the FCM Buffer RAM............................................. 10-70 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Contents Title Page Number xv ...

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... Command Sequence Examples for NAND Flash EEPROM................................... 10-93 10.5.4.1 NAND Flash Soft Reset Command Sequence Example ..................................... 10-94 10.5.4.2 NAND Flash Read Status Command Sequence Example ................................... 10-94 10.5.4.3 NAND Flash Read Identification Command Sequence Example ....................... 10-94 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xvi Contents Title Page Number Freescale Semiconductor ...

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... Outbound Message Registers (OMR0–OMR1)......................................................... 12-5 12.3.5 Doorbell Registers ..................................................................................................... 12-6 12.3.5.1 Outbound Doorbell Register (ODR)...................................................................... 12-6 12.3.5.2 Inbound Doorbell Register (IDR).......................................................................... 12-7 12.3.6 Inbound Message Interrupt Status Register (IMISR) ................................................ 12-7 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Contents Title Chapter 11 Sequencer Chapter 12 DMA/Messaging Unit Page Number xvii ...

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... PCI Configuration Access Registers........................................................................ 13-12 13.3.1.1 PCI_CONFIG_ADDRESS .................................................................................. 13-13 13.3.1.2 PCI_CONFIG_DATA.......................................................................................... 13-14 13.3.1.3 PCI Interrupt Acknowledge Register (PCI_INT_ACK)...................................... 13-15 13.3.2 PCI Memory-Mapped Control and Status Registers ............................................... 13-15 13.3.2.1 PCI Error Status Register (PCI_ESR) ................................................................. 13-15 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xviii Contents Title Chapter 13 PCI Bus Interface Page Number Freescale Semiconductor ...

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... Minimum Grant Configuration Register ............................................................. 13-37 13.3.3.23 Maximum Latency Configuration Register ......................................................... 13-38 13.3.3.24 PCI Function Configuration Register .................................................................. 13-38 13.3.3.25 PCI Arbiter Control Register (PCIACR) ............................................................. 13-39 13.3.3.26 Hot Swap Register Block..................................................................................... 13-40 13.3.3.27 PCI Power Management Register 0 (PCIPMR0) ................................................ 13-41 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Contents Title Page Number xix ...

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... Initialization Sequence for Host Mode .................................................................... 13-60 13.5.2 Initialization Sequence for Agent Mode.................................................................. 13-60 14.1 SEC 2.2 Architecture Overview .................................................................................... 14-2 14.1.1 Descriptors ................................................................................................................. 14-3 14.1.2 Execution Units (EUs) ............................................................................................... 14-5 14.1.2.1 Data Encryption Standard Execution Unit (DEU)................................................. 14-5 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev Contents Title Chapter 14 Security Engine (SEC) 2.2 Page Number Freescale Semiconductor ...

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... MDEU Interrupt Status Register (MDEUISR).................................................... 14-35 14.4.2.8 MDEU Interrupt Control Register (MDEUICR) ................................................. 14-36 14.4.2.9 MDEU ICV Size Register ................................................................................... 14-37 14.4.2.10 MDEU End-of-Message Register (MDEUEMR)................................................ 14-38 14.4.2.11 MDEU Context Registers .................................................................................... 14-38 14.4.2.12 MDEU Key Registers .......................................................................................... 14-39 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Contents Title Page Number xxi ...

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... Master Write ........................................................................................................ 14-66 14.6.3 Controller Interrupts ................................................................................................ 14-66 14.6.4 Controller Registers ................................................................................................. 14-67 14.6.4.1 EU Assignment Status Register (EUASR) .......................................................... 14-67 14.6.4.2 Interrupt Mask Register (IMR)............................................................................ 14-68 14.6.4.3 Interrupt Status Register (ISR) ............................................................................ 14-70 14.6.4.4 Interrupt Clear Register (ICR) ............................................................................. 14-71 14.6.4.5 Identification Register (ID).................................................................................. 14-73 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xxii Contents Title Page Number Freescale Semiconductor ...

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... Transmit Buffer Descriptor Pointers 0–7 (TBPTR0–TBPTR7) ...................... 15-45 15.5.3.2.10 Transmit Descriptor Base Address Registers (TBASE0–TBASE7) ............... 15-46 15.5.3.2.11 Transmit Timestamp Identification Register (TMR_TXTS1–2_ID)............... 15-47 15.5.3.2.12 Transmit Timestamp Register (TMR_TXTS1–2_H/L) ................................... 15-47 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Contents Title Chapter 15 Page Number xxiii ...

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... MAC Exact Match Address 1–15 Part 1 Registers (MAC01ADDR1–MAC15ADDR1)............................................................ 15-78 15.5.3.5.16 MAC Exact Match Address 1–15 Part 2 Registers (MAC01ADDR2–MAC15ADDR2)............................................................ 15-79 15.5.3.6 MIB Registers...................................................................................................... 15-79 15.5.3.6.1 Transmit and Receive 64-Byte Frame Counter (TR64) .................................. 15-80 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xxiv Contents Title Page Number Freescale Semiconductor ...

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... Transmit Drop Frame Counter (TDRP)........................................................... 15-97 15.5.3.6.38 Transmit Jabber Frame Counter (TJBR) ......................................................... 15-98 15.5.3.6.39 Transmit FCS Error Counter (TFCS) .............................................................. 15-98 15.5.3.6.40 Transmit Control Frame Counter (TXCF)....................................................... 15-99 15.5.3.6.41 Transmit Oversize Frame Counter (TOVR) .................................................... 15-99 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Contents Title Page Number xxv ...

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... Encoding............................................................................................ 15-122 15.5.4.1.3 Preamble Shortening...................................................................................... 15-122 15.5.4.2 TBI Receive Process.......................................................................................... 15-122 15.5.4.2.1 Synchronization ............................................................................................. 15-123 15.5.4.2.2 Auto-Negotiation for 1000BASE-X.............................................................. 15-123 15.5.4.3 TBI MII Set Register Descriptions .................................................................... 15-123 15.5.4.3.1 Control Register (CR).................................................................................... 15-124 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xxvi Contents Title Page Number Freescale Semiconductor ...

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... Interrupt Coalescing By Frame Count Threshold.......................................... 15-156 15.6.2.10.3 Interrupt Coalescing By Timer Threshold ..................................................... 15-157 15.6.2.11 Inter-Frame Gap Time ....................................................................................... 15-158 15.6.2.12 Internal and External Loop Back ....................................................................... 15-158 15.6.2.13 Error-Handling Procedure.................................................................................. 15-158 15.6.3 TCP/IP Off-Load ................................................................................................... 15-160 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Contents Title Page Number xxvii ...

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... Transmit Data Buffer Descriptors (TxBD) ........................................................ 15-186 15.6.7.3 Receive Buffer Descriptors (RxBD).................................................................. 15-190 15.7 Initialization/Application Information ....................................................................... 15-192 15.7.1 Interface Mode Configuration ............................................................................... 15-192 15.7.1.1 MII Interface Mode............................................................................................ 15-193 15.7.1.2 RGMII Interface Mode ...................................................................................... 15-196 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xxviii Contents Title Page Number Freescale Semiconductor ...

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... Port Status and Control Register (PORTSC) ....................................................... 16-26 16.3.2.15 On-The-Go Status and Control (OTGSC)—Non-EHCI...................................... 16-31 16.3.2.16 USB Mode Register (USBMODE)—Non-EHCI ................................................ 16-34 16.3.2.17 Endpoint Setup Status Register (ENDPTSETUPSTAT)—Non-EHCI ................ 16-35 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Contents Title Chapter 16 Universal Serial Bus Interface Page Number xxix ...

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... Queue Head Horizontal Link Pointer .................................................................. 16-62 16.5.6.2 Endpoint Capabilities/Characteristics.................................................................. 16-63 16.5.6.3 Transfer Overlay .................................................................................................. 16-65 16.5.7 Periodic Frame Span Traversal Node (FSTN)......................................................... 16-66 16.5.7.1 FTSN Normal Path Pointer.................................................................................. 16-67 16.5.7.2 FSTN Back Path Link Pointer ............................................................................. 16-67 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xxx Contents Title Page Number Freescale Semiconductor ...

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... Rebalancing the Periodic Schedule ............................................................... 16-104 16.6.12.3 Split Transaction Isochronous ........................................................................... 16-104 16.6.12.3.1 Split Transaction Scheduling Mechanisms for Isochronous ......................... 16-105 16.6.12.3.2 Tracking Split Transaction Progress for Isochronous Transfers.................... 16-108 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Contents Title Page Number xxxi ...

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... Stalling ........................................................................................................... 16-133 16.8.3.2 Data Toggle........................................................................................................ 16-134 16.8.3.2.1 Data Toggle Reset.......................................................................................... 16-134 16.8.3.2.2 Data Toggle Inhibit ........................................................................................ 16-134 16.8.3.3 Device Operational Model For Packet Transfers .............................................. 16-135 16.8.3.3.1 Priming Transmit Endpoints.......................................................................... 16-135 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xxxii Contents Title Page Number Freescale Semiconductor ...

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... Periodic Transaction Scheduling and Buffer Management ........................... 16-151 16.9.1.5.5 Multiple Transaction Translators................................................................... 16-152 16.9.2 Device Operation ................................................................................................... 16-152 16.9.3 Non-Zero Fields the Register File ......................................................................... 16-152 16.9.4 SOF Interrupt ......................................................................................................... 16-152 16.9.5 Embedded Design .................................................................................................. 16-153 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Contents Title Page Number xxxiii ...

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... Control Transfer—Implementation Details ..................................................... 17-12 17.4.1.6 Address Compare—Implementation Details ....................................................... 17-13 17.4.2 Arbitration Procedure .............................................................................................. 17-13 17.4.2.1 Arbitration Control .............................................................................................. 17-14 17.4.3 Handshaking ............................................................................................................ 17-14 17.4.4 Clock Control........................................................................................................... 17-14 17.4.4.1 Clock Synchronization......................................................................................... 17-15 17.4.4.2 Input Synchronization and Digital Filter ............................................................. 17-15 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xxxiv Contents Title Chapter Interfaces Page Number Freescale Semiconductor ...

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... Line Control Registers (ULCR1 and ULCR2) .................................................... 18-11 18.3.1.8 MODEM Control Registers (UMCR1 and UMCR2).......................................... 18-13 18.3.1.9 Line Status Registers (ULSR1 and ULSR2) ....................................................... 18-14 18.3.1.10 MODEM Status Registers (UMSR1 and UMSR2) ............................................. 18-15 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Contents Title Chapter 18 DUART Page Number xxxv ...

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... Memory Map/Register Definition ................................................................................. 19-8 19.4.1 Register Descriptions................................................................................................. 19-9 19.4.1.1 SPI Mode Register (SPMODE) ............................................................................. 19-9 19.4.1.2 SPI Event Register (SPIE) ................................................................................... 19-11 19.4.1.3 SPI Mask Register (SPIM) .................................................................................. 19-12 19.4.1.4 SPI Command Register (SPCOM) ...................................................................... 19-14 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xxxvi Contents Title Chapter 19 Serial Peripheral Interface Page Number Freescale Semiconductor ...

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... GPIO Interrupt Mask Register (GPIMR)................................................................... 21-4 21.3.6 GPIO Interrupt Control Register (GPICR) ................................................................ 21-5 A.1 Changes From Revision 1 to Revision 2 ........................................................................ A-1 A.2 Changes From Revision 0 to Revision 1 ...................................................................... A-23 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Contents Title Chapter 20 JTAG/Testing Support Chapter 21 General Purpose I/O (GPIO) Appendix A ...

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... Paragraph Number MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xxxviii Contents Title Page Number Freescale Semiconductor ...

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... DDR Local Access Window n Base Address Registers (DDRLAWBAR0– DDRLAWBAR1) ............................................................................................................. 5-12 5-9 DDR Local Access Window n Attributes Registers (DDRLAWAR0–DDRLAWAR1) ....... 5-13 5-10 System General Purpose Register Low (SGPRL)................................................................. 5-17 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Figures Title Figures Page Number xxxix ...

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... Global Timers Prescale Registers (GTPSR1–GTPSR4)........................................................ 5-60 5-48 Timers Non-Cascaded Mode Block Diagram ....................................................................... 5-62 5-49 Timer Pair-Cascaded Mode Block Diagram ......................................................................... 5-63 5-50 Timers Super-Cascaded Mode Block Diagram..................................................................... 5-63 5-51 Power Management Controller Configuration Register ....................................................... 5-66 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev Figures Title Page Number Freescale Semiconductor ...

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... System External Interrupt Control Register (SECNR) ......................................................... 8-21 8-16 System Error Status Register (SERSR)................................................................................. 8-22 8-17 System Error Mask Register (SERMR) ................................................................................ 8-24 8-18 System Error Control Register (SERCR).............................................................................. 8-24 8-19 System Internal Interrupt Force Register (SIFCR_H) .......................................................... 8-25 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Figures Title Page Number xli ...

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... DDR SDRAM Bank Staggered Auto Refresh Timing.......................................................... 9-45 9-31 DDR SDRAM Power-Down Mode ...................................................................................... 9-46 9-32 DDR SDRAM Self-Refresh Entry Timing ........................................................................... 9-47 9-33 DDR SDRAM Self-Refresh Exit Timing ............................................................................. 9-47 10-1 Enhanced Local Bus Controller Block Diagram................................................................... 10-1 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xlii Figures Title Page Number Freescale Semiconductor ...

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... GPCM Relaxed Timing Back-to-Back Reads (XACS = 0, ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1, EHTR = 0, CLKDIV = 4, 8) ..................................... 10-52 10-38 GPCM Relaxed Timing Back-to-Back Writes (XACS = 0, ACS = 1x, SCY = 0, CSNT = 0, TRLX = 1, CLKDIV = 4, 8) ........................................................ 10-52 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Figures Title Page Number xliii ...

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... RAM Array and Signal Generation .................................................................................... 10-78 10-64 RAM Word Fields ............................................................................................................... 10-79 10-65 LCSn Signal Selection ........................................................................................................ 10-82 10-66 LBS Signal Selection .......................................................................................................... 10-83 10-67 UPM Read Access Data Sampling...................................................................................... 10-86 10-68 Effect of LUPWAIT Signal ................................................................................................. 10-87 10-69 Multiplexed Address/Data Bus for 26-Bit Addressing ....................................................... 10-88 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xliv Figures Title Page Number Freescale Semiconductor ...

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... DMA General Status Register (DMAGSR)........................................................................ 12-15 12-18 DMA Controller Block Diagram ........................................................................................ 12-16 12-19 DMA Chain of Segment Descriptors .................................................................................. 12-19 13-1 PCI Controller Block Diagram ............................................................................................. 13-2 13-2 PCI Interface External Signals.............................................................................................. 13-5 13-3 PCI_CONFIG_ADDRESS Register ................................................................................... 13-13 13-4 PCI_CONFIG_DATA ......................................................................................................... 13-15 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Figures Title Page Number xlv ...

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... Minimum Grant Configuration Register............................................................................. 13-38 13-41 Maximum Latency Configuration Register ........................................................................ 13-38 13-42 PCI Function Configuration Register ................................................................................. 13-38 13-43 PCI Arbiter Control Register (PCIACR) ............................................................................ 13-39 13-44 Hot Swap Register Block .................................................................................................... 13-40 13-45 PCI Power Management Register 0 (PCIPMR0)................................................................ 13-41 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xlvi Figures Title Page Number Freescale Semiconductor ...

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... AESU Data Size Register (AESUDSR).............................................................................. 14-43 14-29 AESU Reset Control Register (AESURCR)....................................................................... 14-43 14-30 AESU Status Register (AESUSR) ...................................................................................... 14-44 14-31 AESU Interrupt Status Register (AESUISR)...................................................................... 14-45 14-32 AESU Interrupt Control Register (AESUICR) ................................................................... 14-47 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Figures Title Page Number xlvii ...

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... TBASE Register Definition ................................................................................................ 15-46 15-20 TMR_TXTSn_ID Register Definition ................................................................................ 15-47 15-21 TMR_TXTSn_H/L Register Definition.............................................................................. 15-47 15-22 RCTRL Register Definition ................................................................................................ 15-48 15-23 RSTAT Register Definition ................................................................................................. 15-50 15-24 RXIC Register Definition ................................................................................................... 15-52 15-25 RQUEUE Register Definition............................................................................................. 15-53 15-26 RBIFX Register Definition ................................................................................................. 15-54 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xlviii Figures Title Page Number Freescale Semiconductor ...

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... Receive Control Frame Packet Counter Register Definition .............................................. 15-85 15-65 Receive Pause Frame Packet Counter Register Definition ................................................. 15-86 15-66 Receive Unknown OPCode Packet Counter Register Definition ....................................... 15-86 15-67 Receive Alignment Error Counter Register Definition....................................................... 15-87 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Figures Title Page Number xlix ...

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... RFBPTR0–RFBPTR7 Register Definition........................................................................ 15-110 15-105 TMR_CTRL Register Definition .......................................................................................15-111 15-106 TMR_TEVENT Register Definition................................................................................. 15-113 15-107 TMR_PEVENT Register Definition................................................................................. 15-115 15-108 TMR_PEMASK Register Definition ................................................................................ 15-116 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev Figures Title Page Number Freescale Semiconductor ...

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... Buffer Descriptor Ring...................................................................................................... 15-186 15-146 Transmit Buffer Descriptor ............................................................................................... 15-187 15-147 Mapping of TxBDs Data Structure......................................................................... 15-187 15-148 Receive Buffer Descriptor................................................................................................. 15-190 15-149 Mapping of RxBDs Data Structure ........................................................................ 15-191 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Figures Title Page Number li ...

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... Frame List Link Pointer Format.......................................................................................... 16-48 16-37 Asynchronous Schedule Organization ................................................................................ 16-49 16-38 Isochronous Transaction Descriptor (iTD) ......................................................................... 16-50 16-39 Split-Transaction Isochronous Transaction Descriptor (siTD) ........................................... 16-53 16-40 Queue Element Transfer Descriptor (qTD)......................................................................... 16-57 16-41 Queue Head Layout ............................................................................................................ 16-62 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 lii Figures Title Page Number Freescale Semiconductor ...

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... Cn Data Register (I2CnDR) ............................................................................................... 17 Digital Filter Sampling Rate Register (I2CnDFSRR) .................................................. 17 Interface Transaction Protocol...................................................................................... 17-10 17-9 EEPROM Contents ............................................................................................................. 17-17 17-10 EEPROM Data Format for One Register Preload Command............................................. 17-18 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Figures Title Page Number liii ...

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... GPIO Open Drain Register (GPODR) .................................................................................. 21-3 21-4 GPIO Data Register (GPDAT) .............................................................................................. 21-4 21-5 GPIO Interrupt Event Register (GPIER) .............................................................................. 21-4 21-6 GPIO Interrupt Mask Register (GPIMR).............................................................................. 21-5 21-7 GPIO Interrupt Control Register (GPICR) ........................................................................... 21-5 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 liv Figures Title Page Number Freescale Semiconductor ...

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... Examples For Hard-Coded Reset Configuration Words Usage............................................ 4-27 4-26 Configurable Clock Units ..................................................................................................... 4-31 4-27 Reset Configuration and Status Registers Memory Map...................................................... 4-32 4-28 Reset Status Register Field Descriptions .............................................................................. 4-33 4-29 RMR Field Descriptions ....................................................................................................... 4-35 4-30 RPR Bit Descriptions ............................................................................................................ 4-36 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Tables Title Tables Page Number lv ...

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... SICRH Bit Settings ............................................................................................................... 5-24 5-29 SICRH[30–31] Bit Settings .................................................................................................. 5-26 5-30 DDRCDR Field Descriptions................................................................................................ 5-27 5-31 DDRDSR Field Descriptions ................................................................................................ 5-28 5-32 WDT Register Address Map................................................................................................. 5-30 5-33 SWCRR Bit Settings ............................................................................................................. 5-31 5-34 SWCNR Bit Settings............................................................................................................. 5-32 5-35 SWSRR Bit Settings ............................................................................................................. 5-33 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 lvi Tables Title Page Number Freescale Semiconductor ...

Page 57

... PCI Bus Power Management State Support.......................................................................... 5-75 5-73 Software-Controller Power-Down States—Basic Description ............................................. 5-76 5-74 MPC8313E Agent Mode Wake-Up Support......................................................................... 5-80 5-75 MPC8313E Host Mode Wake-Up Support ........................................................................... 5-82 6-1 Arbiter Register Map .............................................................................................................. 6-2 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Tables Tables Title Page Number lvii ...

Page 58

... SICNR Field Descriptions .................................................................................................... 8-17 8-16 SEPNR Field Descriptions.................................................................................................... 8-18 8-17 SMPRR_A Field Descriptions .............................................................................................. 8-19 8-18 SMPRR_B Field Descriptions .............................................................................................. 8-20 8-19 SEMSR Field Descriptions ................................................................................................... 8-21 8-20 SECNR Field Descriptions ................................................................................................... 8-22 8-21 SERSR/SERMR/SERFR Bit Assignments ........................................................................... 8-23 8-22 SERSR Field Descriptions .................................................................................................... 8-23 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 lviii Tables Title Page Number Freescale Semiconductor ...

Page 59

... Example of Address Multiplexing for 32-Bit Data Bus Interleaving Between Two Banks with Partial Array Self Refresh Disabled...................................................... 9-36 9-30 DDR SDRAM Command Table............................................................................................ 9-38 9-31 DDR SDRAM Interface Timing Intervals ............................................................................ 9-39 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Tables Tables Title Page Number lix ...

Page 60

... Boot Bank Field Values after Reset for GPCM as Boot Controller.................................... 10-56 10-35 FCM Chip-Select to First Command Timing...................................................................... 10-65 10-36 FCM Command, Address, and Write Data Timing Parameters.......................................... 10-66 10-37 FCM Read Data Timing Parameters ................................................................................... 10-69 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev Tables Title Page Number Freescale Semiconductor ...

Page 61

... DMA Segment Descriptor Fields........................................................................................ 12-18 13-1 PCI Controller Modes ........................................................................................................... 13-3 13-2 Signal Properties ................................................................................................................... 13-4 13-3 PCI Interface Signals—Detailed Signal Descriptions .......................................................... 13-5 13-4 PCI Configuration Access Registers................................................................................... 13-11 13-5 PCI Memory-Mapped Registers ......................................................................................... 13-12 13-6 PCI_CONFIG_ADDRESS Field Descriptions ................................................................... 13-13 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Tables Tables Title Page Number lxi ...

Page 62

... PCI Arbiter Control Register (PCIACR) Field Descriptions.............................................. 13-39 13-42 Hot Swap Register Block Field Descriptions ..................................................................... 13-40 13-43 PCIPMR0 Field Descriptions.............................................................................................. 13-41 13-44 PCIPMR1 Field Descriptions.............................................................................................. 13-42 13-45 PCI Command Definitions.................................................................................................. 13-46 13-46 Special Cycle Commands ................................................................................................... 13-56 14-1 Example Descriptor............................................................................................................... 14-4 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 lxii Tables Title Page Number Freescale Semiconductor ...

Page 63

... Field Names in Interrupt Mask, Interrupt Status, and Interrupt Clear Registers ................ 14-70 14-40 MCR Field Descriptions ..................................................................................................... 14-74 15-1 eTSECn Network Interface Signal Properties ...................................................................... 15-6 15-2 eTSEC Signals—Detailed Signal Descriptions .................................................................... 15-8 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Tables Tables Title Page Number lxiii ...

Page 64

... RBDBPH Field Descriptions .............................................................................................. 15-62 15-37 RBPTRn Field Descriptions................................................................................................ 15-63 15-38 RBASE0–RBASE7 Field Descriptions .............................................................................. 15-63 15-39 TMR_RXTS_H/L Register Field Descriptions................................................................... 15-64 15-40 MACCFG1 Field Descriptions ........................................................................................... 15-67 15-41 MACCFG2 Field Descriptions ........................................................................................... 15-69 15-42 IPGIFG Field Descriptions ................................................................................................. 15-70 15-43 HAFDUP Field Descriptions .............................................................................................. 15-71 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 lxiv Tables Title Page Number Freescale Semiconductor ...

Page 65

... RFRG Field Descriptions.................................................................................................... 15-90 15-78 RJBR Field Descriptions..................................................................................................... 15-90 15-79 RDRP Field Descriptions.................................................................................................... 15-91 15-80 TBYT Field Descriptions.................................................................................................... 15-91 15-81 TPKT Field Descriptions .................................................................................................... 15-92 15-82 TMCA Field Descriptions................................................................................................... 15-92 15-83 TBCA Field Descriptions.................................................................................................... 15-93 15-84 TXPF Field Descriptions .................................................................................................... 15-93 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Tables Tables Title Page Number lxv ...

Page 66

... TMR_ALARMn_H/L Register Field Descriptions .......................................................... 15-120 15-123 TMR_FIPER Register Field Descriptions ........................................................................ 15-121 15-124 TMR_ETTS1-2_H Register Field Descriptions ............................................................... 15-121 15-125 TBI MII Register Set......................................................................................................... 15-123 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 lxvi Tables Title Page Number Freescale Semiconductor ...

Page 67

... Transmit Data Buffer Descriptor (TxBD) Field Descriptions .......................................... 15-188 15-164 Receive Buffer Descriptor Field Descriptions .................................................................. 15-191 15-165 MII Interface Mode Signal Configuration ........................................................................ 15-193 15-166 Shared MII Signals............................................................................................................ 15-194 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Tables Tables Title Page Number lxvii ...

Page 68

... OTGSC Register Field Descriptions................................................................................... 16-32 16-25 USBMODE Register Field Descriptions ............................................................................ 16-34 16-26 ENDPTSETUPSTAT Register Field Descriptions.............................................................. 16-35 16-27 ENDPTPRIME Register Field Descriptions ....................................................................... 16-35 16-28 ENDPTFLUSH Register Field Descriptions....................................................................... 16-36 16-29 ENDPTSTATUS Register Field Descriptions ..................................................................... 16-37 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 lxviii Tables Title Page Number Freescale Semiconductor ...

Page 69

... Interrupt IN/OUT Do Complete Split State Execution Criteria........................................ 16-103 16-69 Initial Conditions for OUT siTD TP and T-Count Fields ..................................................16-111 16-70 Transaction Position (TP)/Transaction Count (T-Count) Transition Table........................16-111 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Tables Tables Title Page Number ...

Page 70

... I2CnCR Field Descriptions ................................................................................................... 17-7 17-7 I2CnSR Field Descriptions ................................................................................................... 17-8 17-8 I2CnDR Field Descriptions................................................................................................... 17-9 17-9 I2CnDFSRR Field Descriptions.......................................................................................... 17-10 18-1 DUART Signal Overview ..................................................................................................... 18-3 18-2 DUART Signals—Detailed Signal Descriptions .................................................................. 18-3 18-3 DUART Register Summary .................................................................................................. 18-4 18-4 URBR Field Descriptions ..................................................................................................... 18-6 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 lxx Tables Title Page Number Freescale Semiconductor ...

Page 71

... IPIC External Signals—Detailed Signal Descriptions.......................................................... 21-2 21-2 GPIO Register Address Map................................................................................................. 21-2 21-3 GPDIR Bit Settings ............................................................................................................... 21-3 21-4 GPODR Bit Settings ............................................................................................................. 21-3 21-5 GPnDAT Bit Settings ............................................................................................................ 21-4 21-6 GPIER Bit Settings ............................................................................................................... 21-4 21-7 GPIMR Bit Settings .............................................................................................................. 21-5 21-8 GPICR Bit Settings ............................................................................................................... 21-5 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Tables Tables Title Page Number lxxi ...

Page 72

... Table Number MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 lxxii Tables Title Page Number Freescale Semiconductor ...

Page 73

... MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor provides a high-level description of features and functionality of the describes the memory map of the MPC8313E. An overview of the ...

Page 74

... I/O sequencer (IOS) switches transactions among its ,” describes the four-channel high speed general-purpose describes the PCI interface, which complies with the PCI Local describes the SEC 2.2, which is designed to offload describes the IPIC interrupt describes the two enhanced Freescale Semiconductor ...

Page 75

... Computer Organization and Design: The Hardware/Software Interface, Second Edition, by David A. Patterson and John L. Hennessy. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor describes the universal serial bus (USB) interface. describes the inter-IC (IIC or I describes the (dual) universal asynchronous receiver/transmitters ...

Page 76

... In some contexts, such as signal encodings, an unitalicized x indicates a don’t care x An italicized x indicates an alphanumeric variable n An italicized n indicates a numeric variable ¬ NOT logical operator MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 lxxvi Freescale Semiconductor ...

Page 77

... Cyclic redundancy check CRS Carrier sense CSB Coherent system bus CSMA Carrier-sense multiple access MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Section 3.2, “Configuration Signals Sampled at Reset.” Table i. Acronyms and Abbreviated Terms Meaning About This Book lxxvii ...

Page 78

... Joint Test Action Group LALE LBC external address latch enable LBC Local bus controller LRU Least recently used LSB Least-significant byte lsb Least-significant bit LSU Load/store unit MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 lxxviii Meaning Freescale Semiconductor ...

Page 79

... Real time clock module Rx Receive RxBD Receive buffer descriptor SCL Serial clock SDA Serial data SFD Start frame delimiter SGMII Serial gigabit media independent interface MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Meaning About This Book lxxix ...

Page 80

... USB low-pin count interface UPM User-programmable machine USB Universal serial bus UTMI USB transceiver macrocell interface UTP Unshielded twisted pair WDT Watchdog timer ZBT Zero bus turnaround MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 lxxx Meaning Freescale Semiconductor ...

Page 81

... Dual I2C Timers Interrupt GPIO Controller SPI I/O Sequencer (IOS) PCI DMA MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 2 C controllers, a 4-channel DMA controller, a general-purpose e300c3 Core with FPU and Power Management 16-KB 16-KB I-Cache D-Cache USB 2.0 HS Security Engine 2.2 ...

Page 82

... Fetch FIFOs in the crypto-channel • DDR SDRAM memory controller — Programmable timing supporting both DDR1 and DDR2 SDRAM — 16-/32-bit data interface 333-MHz data rate — 512-Mbyte addressable space MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 1-2 Freescale Semiconductor ...

Page 83

... Full- and half-duplex Ethernet support (1000 Mbps supports only full-duplex): – IEEE Std. 802.3 full-duplex flow control (automatic PAUSE frame generation or software-programmed PAUSE frame generation and recognition) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Overview 1-3 ...

Page 84

... Universal serial bus (USB) dual-role controller — Designed to comply with Universal Serial Bus Revision 2.0 Specification — Supports operation as a stand-alone USB host controller – Supports USB root hub with one downstream-facing port MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 1-4 Freescale Semiconductor ...

Page 85

... Unique vector number for each interrupt source 2 • Dual I C interfaces — Each controller operates up to 400 kHz — Two-wire interface — Multiple-master support 2 — Master or slave I C mode support MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Overview 1-5 ...

Page 86

... Periodic interrupt timer — Real-time clock — Software watchdog timer — Two general-purpose timers • IEEE Std. 1149.1™ compliant JTAG boundary scan • Integrated PCI bus and SDRAM clock generation MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 1-6 Freescale Semiconductor ...

Page 87

... As an added feature to the e300 core, the device can lock the contents of three of the four ways in the instruction and data cache (or an entire cache). For example, this allows embedded applications to lock MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Overview 1-7 ...

Page 88

... IU2, FPU, BPU, LSU, and SRU) operate independently and in parallel. Note that this is a conceptual diagram and does not attempt to show how these features are physically implemented on the chip. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 1-8 Freescale Semiconductor ...

Page 89

... Control Decrementer JTAG/COP Clock Multiplier Interface Touch Load Buffer Copy-Back Buffer Figure 1-2. MPC8313E Integrated e300c3 Core Block Diagram MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 64-Bit Sequential Processing Fetcher 64-Bit Instruction Queue 64-Bit Dispatch Unit Instruction Unit ...

Page 90

... Support for DDR1 and DDR2 SDRAM • 16- or 32-bit SDRAM data bus • Programmable settings for meeting all SDRAM timing parameters MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 1-10 FIFO Control DEU AESU FIFO Figure 1-3. The bus interface FIFO MDEU Freescale Semiconductor ...

Page 91

... On receive, packets may be distributed to any of the 64 virtual receive queues overlaid onto the 8 physical receive queues. A table-oriented queue filing strategy is provided based on 16 header fields or flags. Frame rejection is supported for filtering applications. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Overview 1-11 ...

Page 92

... MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 1-12 NOTE eTSEC1 TBI, GMII, or MII RTBI, RGMII, or RMII 8-bit FIFO RTBI, RGMII, RMII, or 8-bit FIFO TBI, GMII, MII, RTBI, RGMII, RMII, or 8-bit FIFO 1 eTSEC2 TBI, GMII, or MII RTBI, RGMII, or RMII 8-bit FIFO Freescale Semiconductor ...

Page 93

... The host and device functions are both configured to support the following four types of USB transfers: • Bulk • Control • Interrupt • Isochronous Figure 1-4. USB Controllers Port Configuration MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor CSB TX Buffer Dual-Role Module (DR) RX Buffer DR Mux On-Chip PHY Overview Figure 1-4 ...

Page 94

... Data buffer controls activated on a per-bank basis — 256-byte bursts, arbitrarily aligned — Automatic segmentation of large transactions into memory accesses optimized for bus width and addressing capability MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 1-14 Freescale Semiconductor ...

Page 95

... Internal address multiplexing supporting 64-, 128-, 256-, and 512-Kbyte, and 1-, 2-, 4-, 8-, 16-, 32-, 64-, 128-, and 256-Mbyte page banks • Optional monitoring of transfers between local bus internal masters and local bus slaves (local bus error reporting) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Overview 1-15 ...

Page 96

... Software-selectable acknowledge bit • On-chip filtering for spikes on the bus • Address broadcasting supported MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev controller consists unit supports general broadcast mode and Freescale Semiconductor C allows the ...

Page 97

... Software-selectable serial-interface data format (data length, parity, 1/1.5/2 STOP bit, baud rate) • Line status registers • Line-break detection and generation MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 2 C EPROM by boot sequencer embedded Overview 16 – 1) and 1-17 ...

Page 98

... Two general-purpose timer blocks, each supporting four 16-bit programmable timers, two cascaded 32-bit timers, or one cascaded 64-bit counter 1.3 Application Examples The internal features of the MPC8313E make it suitable for a wide variety of printer and network communication applications as described in this section. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 1-18 Freescale Semiconductor ...

Page 99

... ASIC lower cost without the need to have separate a CPU and interface ASIC. At the same time, the system is required to consume low power. The MPC8313E provides several power management methods to reduce power consumption. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Color Match DDR ...

Page 100

... Once the I/O processor detects data transfer through the LAN, USB and PCI or an interrupt from the push of a button on the panel, it quickly boots up the main CPU. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 1-20 DDR MPC8313E SDRAM PCI 32-Bit/66 M PCI PCI to PCI Main ASIC Freescale Semiconductor ...

Page 101

... The trigger inputs and outputs enable coordination of other devices. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Remote Test Controller Trigger In ...

Page 102

... Target applications for systems with IEEE Std. 1588 are test and measurement appliances and industrial control and automation. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 1-22 Switch Servo Drive Servo Drive Servo Drive Switch MPC8313E Servo Drive MPC8313E Servo Drive Freescale Semiconductor ...

Page 103

... WAPs deployed throughout the premise. Power is drawn from the AC outlet in the wall or power over Ethernet. Having an SGMII interface on the Gigabit Ethernet PHYs enables low overall power consumption. The MPC8313E also has superior PCI to memory performance. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor eTSEC MPC8313E eTSEC Overview 802 ...

Page 104

... MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 1-24 Hard Drive IDE/SATA 802.11 Audio MPEG Decode PCI IR LEDs Display Processor 2D Graphics Figure 1-10. MPC8313E as a Media Server LAN Connection Flash Memory Ethernet DDR2 Security PCI MPC8313E USB Hard Drive or External CE Device Freescale Semiconductor ...

Page 105

... This would allow for maintaining the legacy functionality when set to zero. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Section 5.2.4.1, “Internal Memory Map Registers Base Address 2-1 ...

Page 106

... Kbyte — 1 Kbyte — 1 Kbyte 4 Kbytes 24 bytes 256 bytes 24 bytes 256 bytes — 256 bytes — 256 bytes — 1 Kbyte — 1 Kbyte Freescale Semiconductor ...

Page 107

... Reserved 0x1_A000–0x1_BFFF Reserved 0x1_C000–0x1_FFFF Reserved 0x2_0000–0x2_1FFF Reserved 0x2_2000–0x2_2FFF Reserved 0x2_3000–0x2_3FFF USB_DR module MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Table 2-1. IMMR Memory Map (continued) Use Memory Map Actual Size Window — ...

Page 108

... Kbytes — 128 Kbytes — 8 Kbytes — 4 Kbytes — 256 bytes — 256 bytes — 512 bytes — 1 Kbyte — 2 Kbytes — 16 Kbytes — 32 Kbytes — 64 Kbytes Reset Section/Page R/W 0xFF40_0000 5.2.4.1/5-6 — — — R/W 0x0000_0000 5.2.4.2/5-7 — — — 1 R/W 0x0000_0000 5.2.4.3/5-8 Freescale Semiconductor ...

Page 109

... System part and revision ID register (SPRIDR) 0x0010C Reserved 0x00110 System priority configuration register (SPCR) 0x00114 System I/O configuration register low (SICRL) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Table 2-2. Memory Map (continued) Register Access Memory Map Reset Section/Page 2 ...

Page 110

... R/W 0xFFFF_0003 5.4.4.1/5- 0xFFFF_0007 R 0x0000_FFFF 5.4.4.2/5-32 — — — R/W 0x0000 5.4.4.3/5-33 R/W 0x0000_0000 5.5.5.1/5-38 R/W 0x0000_0000 5.5.5.2/5-39 R/W 0x0000_0000 5.5.5.3/5-40 R 0x0000_0000 5.5.5.4/5-40 w1c 0x0000_0000 5.5.5.5/5-41 R/W 0xFFFF_FFFF 5.5.5.6/5-41 — — R/W 0x0000_0000 5.6.5.1/5-45 R/W 0x0000_0000 5.6.5.2/5-46 R/W 0x0000_0000 5.6.5.3/5-47 R 0x0000_0000 5.6.5.4/5-47 w1c 0x0000_0000 5.6.5.5/5-47 — — R/W 0x00 5.7.5.1/5-55 — — — Freescale Semiconductor ...

Page 111

... System internal interrupt pending register (SIPNR_H) 0x0C System internal interrupt pending register (SIPNR_L) 0x10 System internal interrupt group A priority register (SIPRR_A) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Table 2-2. Memory Map (continued) Register Access Memory Map Reset Section/Page ...

Page 112

... Reset Section/Page R/W 0x0530_9770 8.5.5/8-14 R/W 0x0000_0000 8.5.6/8-15 R/W 0x0000_0000 8.5.6/8-15 R/W 0x0000_0000 8.5.7/8-16 R/W Special 8.5.8/8-18 R/W 0x0530_9770 8.5.9/8-18 R/W 0x0530_9770 8.5.10/8-19 R/W 0x0000_0000 8.5.11/8-20 R/W 0x0000_0000 8.5.12/8-21 R/W 0x0000_0000 8.5.13/8-22 R/W 8.5.14/8-23 R/W 0x0000_0000 8.5.15/8-24 — — — R/W 0x0000_0000 8.5.16/8-25 R/W 0x0000_0000 8.5.16/8-25 R/W 0x0000_0000 8.5.17/8-26 R/W 0x0000_0000 8.5.18/8-26 R 0x0000_0000 8.5.19/8-27 R 0x0000_0000 8.5.20/8-27 — — — R/W 0x0000_0000/ 6.2.1/6-2 10 0x0010_0000 R/W 0xFFFF_FFFF 6.2.2/6-4 w1c 0x0000_0000 6.2.3/6-5 R/W 0x0000_0000 6.2.4/6-6 R/W 0x0000_0000 6.2.5/6 0x0000_0000 6.2.6/6 0x0000_0000 6.2.7/6-9 R/W 0x0000_0000 6.2.8/6-10 R 0x0000_0000 4.5.1.1/4-33 R 0x0000_0000 4.5.1.2/4-33 Freescale Semiconductor ...

Page 113

... CS0_BNDS—Chip select 0 memory bounds 0x008 CS1_BNDS—Chip select 1 memory bounds 0x080 CS0_CONFIG—Chip select 0 configuration MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Table 2-2. Memory Map (continued) Register Access Clock Module Power Management Control Module GPIO Registers ...

Page 114

... R/W 0x0000_0000 9.4.1.3/9-11 R/W 0x0011_0105 9.4.1.4/9-12 R/W 0x0000_0000 9.4.1.5/9-14 R/W 0x0000_0000 9.4.1.6/9-16 R/W 0x0200_0000 9.4.1.7/9-18 R/W 0x0000_0000 9.4.1.8/9-21 R/W 0x0000_0000 9.4.1.9/9-22 R/W 0x0000_0000 9.4.1.10/9-23 R/W 0x0000_0000 9.4.1.11/9-24 R/W 0x0000_0000 9.4.1.12/9-26 R/W 0x0000_0000 9.4.1.13/9-27 R/W 0x0200_0000 9.4.1.14/9-27 — — — R/W 0x0000_0000 9.4.1.15/9-28 — — — nnnn _ nnnn 9.4.1.16/9-28 12 0x00 nn _00 nn R 9.4.1.17/9-29 R/W 0x00 17.3.1.1/17-5 R/W 0x00 17.3.1.2/17-6 R/W 0x00 17.3.1.3/17-7 R/W 0x81 17.3.1.4/17-8 R/W 0x00 17.3.1.5/17-9 R/W 0x10 17.3.1.6/17-9 — — — R/W 0x00 17.3.1.1/17-5 R/W 0x00 17.3.1.2/17-6 R/W 0x00 17.3.1.3/17-7 R/W 0x81 17.3.1.4/17-8 Freescale Semiconductor ...

Page 115

... ULCR—ULCR[DLAB UART2 line control register 0x0_4604 UMCR—ULCR[DLAB UART2 MODEM control register 0x0_4605 ULSR—ULCR[DLAB UART2 line status register MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Table 2-2. Memory Map (continued) Register Access DUART Memory Map ...

Page 116

... R/W 0x0000_0000 10.3.1.1/10-10 R/W 0x0000_0000 10.3.1.1/10-10 R/W 0x0000_0000 10.3.1.1/10-10 R/W 0x0000_0000 10.3.1.1/10-10 R/W 0x0000_0FF7 10.3.1.2/10-11 R/W 0x0000_0000 10.3.1.2/10-11 R/W 0x0000_0000 10.3.1.2/10-11 R/W 0x0000_0000 10.3.1.2/10-11 — — — R/W 0x0000_0000 10.3.1.3/10-19 — — — R/W 0x0000_0000 10.3.1.4/10-20 R/W 0x0000_0000 10.3.1.4/10-20 R/W 0x0000_0000 10.3.1.4/10-20 — — — R/W 0x0000_0000 10.3.1.5/10-22 R/W 0x0000_0000 10.3.1.6/10-22 — — — R/W 0x0000_0000 10.3.1.7/10-23 — — — R/W 0x0000_0000 10.3.1.4/10-20 — — — w1c 0x0000_0000 10.3.1.9/10-25 R/W 0x0000_0000 10.3.1.10/10-27 R/W 0x0000_0000 10.3.1.11/10-28 Freescale Semiconductor ...

Page 117

... Reserved 0xFFF OMISR—Outbound message interrupt status register 0x0_8030 OMIMR—Outbound message interrupt mask register 0x0_8034 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Table 2-2. Memory Map (continued) Register Access Serial Peripheral Interface (SPI) Mixed DMA Registers ...

Page 118

... Table 2-2. Memory Map (continued) Register Access Mixed Reset Section/Page R/W 0x0000_0000 12.3.3/12-5 R/W 0x0000_0000 12.3.3/12-5 R/W 0x0000_0000 12.3.4/12-5 R/W 0x0000_0000 12.3.4/12-5 R/W 0x0000_0000 12.3.5/12-6 R/W 0x0000_0000 12.3.5/12-6 0x0000_0000 12.3.6/12-7 R/W 0x0000_0000 12.3.7/12-8 R/W 0x0000_0000 12.3.8.1/12-9 R/W 0x0000_0000 12.3.8.2/12-11 R/W 0x0000_0000 12.3.8.3/12-12 R/W 0x0000_0000 12.3.8.4/12-13 R/W 0x0000_0000 12.3.8.5/12-13 R/W 0x0000_0000 12.3.8.6/12-14 R/W 0x0000_0000 12.3.8.7/12-14 R/W 0x0000_0000 12.3.8.1/12-9 R/W 0x0000_0000 12.3.8.2/12-11 R/W 0x0000_0000 12.3.8.3/12-12 R/W 0x0000_0000 12.3.8.4/12-13 R/W 0x0000_0000 12.3.8.5/12-13 R/W 0x0000_0000 12.3.8.6/12-14 R/W 0x0000_0000 12.3.8.7/12-14 R/W 0x0000_0000 12.3.8.1/12-9 R/W 0x0000_0000 12.3.8.2/12-11 R/W 0x0000_0000 12.3.8.3/12-12 R/W 0x0000_0000 12.3.8.4/12-13 R/W 0x0000_0000 12.3.8.5/12-13 R/W 0x0000_0000 12.3.8.6/12-14 R/W 0x0000_0000 12.3.8.7/12-14 R/W 0x0000_0000 12.3.8.1/12-9 R/W 0x0000_0000 12.3.8.2/12-11 R/W 0x0000_0000 12.3.8.3/12-12 R/W 0x0000_0000 12.3.8.4/12-13 Freescale Semiconductor ...

Page 119

... POCMR4—PCI outbound comparison mask register 4 0x78 POTAR5—PCI outbound translation address register 5 0x80 POBAR5—PCI outbound base address register 5 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Table 2-2. Memory Map (continued) Register Access PCI Software Configuration Registers Sequencer (IOS) ...

Page 120

... R/W 0x0000_0000 11.4.5/11-6 w1c 0x0000_0000 13.3.2.1/13-15 R/W 0x0000_0000 13.3.2.2/13-16 R/W 0x0000_0000 13.3.2.3/13-17 R/W 0x0000_0000 13.3.2.4/13-18 R 0x0000_0000 13.3.2.5/13-19 R 0x0000_0000 13.3.2.6/13-20 R/W 0x0000_0000 13.3.2.7/13-20 R/W 0x0000_0000 13.3.2.8/13-20 R/W 0x0000_0000 13.3.2.9/13-21 R 0x0000_0000 13.3.2.10/13-22 R/W 0x0000_0000 13.3.2.11/13-22 — — — R/W 0x0000_0000 13.3.2.12/13-23 R/W 0x0000_0000 13.3.2.13/13-24 R/W 0x0000_0000 13.3.2.14/13-24 R/W 0x0000_0000 13.3.2.11/13-22 — — — R/W 0x0000_0000 13.3.2.12/13-23 R/W 0x0000_0000 13.3.2.13/13-24 R/W 0x0000_0000 13.3.2.14/13-24 R/W 0x0000_0000 13.3.2.11/13-22 — — — R/W 0x0000_0000 13.3.2.12/13-23 R/W 0x0000_0000 13.3.2.13/13-24 — — — — — — Freescale Semiconductor ...

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... ENDPTCTRL1—Endpoint control 1 0x2_31C8 ENDPTCTRL2—Endpoint control 2 0x2_31CA– Reserved 0x2_31D4 0x2_3400 SNOOP1—Snoop 1 0x2_3404 SNOOP2—Snoop 2 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Table 2-2. Memory Map (continued) Register Access Mixed Mixed 13 Mixed Mixed ...

Page 122

... R/W 0x0000_0000 15.5.3.1.4/15-27 R/W 0x0000_0000 15.5.3.1.5/15-29 — — — R/W 0x0000_0000 15.5.3.1.6/15-31 — — — R/W 0x0000_0000 15.5.3.1.7/15-33 R/W 0x0000_0000 15.5.3.1.8/15-34 — — — — — — R/W 0x0000_0000 15.5.3.2.1/15-35 w1c 0x0000_0000 15.5.3.2.2/15-37 R/W 0x8100_0000 15.5.3.2.3/15-41 — — — R/W 0x0000_0000 15.5.3.2.4/15-42 R/W 0x0000_8000 15.5.3.2.5/15-43 — — — R/W 0x0000_0000 15.5.3.2.6/15-43 R/W 0x0000_0000 15.5.3.2.7/15-44 — — — R/W 0x0000_0000 15.5.3.2.8/15-45 Freescale Semiconductor ...

Page 123

... Reserved 0x2_423C TBASE7*—TxBD base address of ring 7 0x2_4240– Reserved 0x2_427C 0x2_4280 TMR_TXTS1_ID timestamp identification tag (set 1) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Table 2-2. Memory Map (continued) Register Access Memory Map Reset Section/Page R/W 0x0000_0000 15.5.3.2.9/15-45 — ...

Page 124

... R/W 0x0000_0000 15.5.3.3.3/15-52 R/W 0x0080_0080 15.5.3.3.4/15-53 — — — R/W 0x0000_0000 15.5.3.3.5/15-54 R/W 0x0000_0000 15.5.3.3.6/15-55 R/W 0x nnnn_nnnn 15.5.3.3.7/15-56 R/W 0x nnnn_nnnn 15.5.3.3.8/15-57 R/W 0x0000_0000 15.5.3.3.9/15-61 — — — R/W 0x0000_0000 15.5.3.3.10/15-62 R/W 0x0000_0000 15.5.3.3.11/15-62 — — — R/W 0x0000_0000 15.5.3.3.11/15-62 — — — R/W 0x0000_0000 15.5.3.3.11/15-62 — — — R/W 0x0000_0000 15.5.3.3.11/15-62 — — — R/W 0x0000_0000 15.5.3.3.11/15-62 — — — Freescale Semiconductor ...

Page 125

... IPGIFG—Inter-packet/inter-frame gap register 0x2_450C HAFDUP—Half-duplex control 0x2_4510 MAXFRM—Maximum frame length 0x2_4514– Reserved 0x2_451C MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Table 2-2. Memory Map (continued) Register Access eTSEC MAC Registers Memory Map Reset Section/Page R/W 0x0000_0000 15 ...

Page 126

... MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 2-22 Table 2-2. Memory Map (continued) Register Access Reset Section/Page R/W 0x0000_0007 15.5.3.5.6/15-72 R/W 0x0000_0000 15.5.3.5.7/15-73 R/W 0x0000_0000 15.5.3.5.8/15-74 WO 0x0000_0000 15.5.3.5.9/15-75 R 0x0000_0000 15.5.3.5.10/15-75 R 0x0000_0000 15.5.3.5.11/15-76 — — — R 0x0000_0000 15.5.3.5.12/15-76 R/W 0x0000_0000 15.5.3.5.13/15-77 R/W 0x0000_0000 15.5.3.5.14/15-78 R/W 0x0000_0000 15.5.3.5.15/15-78 15.5.3.5.16/15-79 R/W 0x0000_0000 R/W 0x0000_0000 R/W 0x0000_0000 R/W 0x0000_0000 R/W 0x0000_0000 R/W 0x0000_0000 R/W 0x0000_0000 R/W 0x0000_0000 R/W 0x0000_0000 Freescale Semiconductor ...

Page 127

... TRMGV—Transmit and receive 1519- to 1522-byte good VLAN frame count 0x2_469C RBYT—Receive byte counter MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Table 2-2. Memory Map (continued) Register Access eTSEC Transmit and Receive Counters eTSEC Receive Counters ...

Page 128

... Transmit Counters Reset Section/Page R/W 0x0000_0000 15.5.3.6.9/15-83 R/W 0x0000_0000 15.5.3.6.10/15-84 R/W 0x0000_0000 15.5.3.6.11/15-84 R/W 0x0000_0000 15.5.3.6.12/15-85 R/W 0x0000_0000 15.5.3.6.13/15-85 R/W 0x0000_0000 15.5.3.6.14/15-86 R/W 0x0000_0000 15.5.3.6.15/15-86 R/W 0x0000_0000 15.5.3.6.16/15-87 R/W 0x0000_0000 15.5.3.6.17/15-87 R/W 0x0000_0000 15.5.3.6.18/15-88 R/W 0x0000_0000 15.5.3.6.19/15-88 R/W 0x0000_0000 15.5.3.6.20/15-89 R/W 0x0000_0000 15.5.3.6.21/15-89 R/W 0x0000_0000 15.5.3.6.22/15-90 R/W 0x0000_0000 15.5.3.6.23/15-90 R/W 0x0000_0000 15.5.3.6.24/15-91 R/W 0x0000_0000 15.5.3.6.25/15-91 R/W 0x0000_0000 15.5.3.6.26/15-92 R/W 0x0000_0000 15.5.3.6.27/15-92 R/W 0x0000_0000 15.5.3.6.28/15-93 R/W 0x0000_0000 15.5.3.6.29/15-93 R/W 0x0000_0000 15.5.3.6.30/15-94 R/W 0x0000_0000 15.5.3.6.31/15-94 R/W 0x0000_0000 15.5.3.6.32/15-95 R/W 0x0000_0000 15.5.3.6.33/15-95 R/W 0x0000_0000 15.5.3.6.34/15-96 R/W 0x0000_0000 15.5.3.6.35/15-96 R/W 0x0000_0000 15.5.3.6.36/15-97 — — — R/W 0x0000_0000 15.5.3.6.37/15-97 R/W 0x0000_0000 15.5.3.6.38/15-98 R/W 0x0000_0000 15.5.3.6.39/15-98 R/W 0x0000_0000 15.5.3.6.40/15-99 R/W 0x0000_0000 15.5.3.6.41/15-99 Freescale Semiconductor ...

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... Reserved 0x2_4AFC 0x2_4B00– Reserved 0x2_4BF4 0x2_4BF8 ATTR—Attribute register MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Table 2-2. Memory Map (continued) Register Access 14 14 Hash Function Registers eTSEC DMA Attribute Registers Memory Map Reset ...

Page 130

... R/W 0x0000_0000 15.5.3.9.2/15-109 — — — R/W 0x0000_0000 15.5.3.9.2/15-109 — — — R/W 0x0000_0000 15.5.3.9.2/15-109 — — — R/W 0x0000_0000 15.5.3.9.2/15-109 — — — R/W 0x0000_0000 15.5.3.9.2/15-109 — — — R/W 0x0001_0001 15.5.3.10.1/15-110 W1C 0x0000_0000 15.5.3.10.2/15-112 R/W 0x0000_0000 15.5.3.10.3/15-114 R/W 0x0000_0000 15.5.3.10.4/15-115 R/W 0x0000_0000 15.5.3.10.5/15-115 Freescale Semiconductor ...

Page 131

... REGISTERS 0x2_5FFF 0x3_0000– Reserved, should be cleared 0x3_0FFF 0x3_1008 IMR—Interrupt mask register MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Table 2-2. Memory Map (continued) Register Other eTSECs 15 Security Engine Address Map Registers Controller Registers Access ...

Page 132

... W 0x0000_0000 14.6.4.4/14-71 _0000_0000 R 0000_0000 14.6.4.5/14-73 _0000_00A0 R 0xF0F0_F0F0 14.6.4.1/14-67 _00FF_F0F0 R/W 0000_0000 14.6.4.7/14-74 _0000_0000 R/W 0x0000_0000 14.5.1.1/14-55 _0000_0000 R 0x0000_0000 14.5.1.2/14-57 _0000_0007 R 0x0000_0000 14.5.1.3/14-62 _0000_0000 W 0x0000_0000 14.5.1.4/14-62 _0000_0000 R 0x0000_0000 14.5.1.5/14-63 _0000_0000 R 0x0000_0000 14.6.4.6/14-73 _0002_00A0 R/W 0x0000_0000 14.4.1.1/14-19 _0000_0000 R/W 0x0000_0000 14.4.1.2/14-20 _0000_0000 R/W 0x0000_0000 14.4.1.3/14-21 _0000_0000 R/W 0x0000_0000 14.4.1.4/14-22 _0000_0000 R 0x0000_0000 14.4.1.5/14-23 _0000_0000 R 0x0000_0000 14.4.1.6/14-24 _0000_0000 R/W 0x0000_0000 14.4.1.7/14-25 _0000_3000 W 0x0000_0000 14.4.1.8/14-27 _0000_0000 R/W 0x0000_0000 14.4.1.9/14-27 _0000_0000 Freescale Semiconductor ...

Page 133

... MDEURCR—MDEU reset control register 0x3_6028 MDEUSR—MDEU status register 0x3_6030 MDEUISR—MDEU interrupt status register MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Table 2-2. Memory Map (continued) Register Access Message Digest Execution Unit (MDEU) Memory Map ...

Page 134

... Section 5.2.4.7.1, “DDRLAWBAR0[BASE_ADDR] Reset Value,” Section 5.2.4.6.1, “PCILAWAR0[EN] and PCILAWAR0[SIZE] Reset Section 5.2.4.7.1, “DDRLAWBAR0[BASE_ADDR] Reset Value,” Section 5.2.4.8.1, “DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset Reset Section/Page R/W 0x0000_0000 14.4.2.8/14-36 _0000_1000 R/W 0x0000_0000_0 14.4.2.9/14-37 000_0000 W 0x0000_0000 14.4.2.10/14-38 _0000_0000 R/W 0x0000_0000 14.4.2.11/14-38 _0000_0000 W 0x0000_0000 14.4.2.12/14-39 _0000_0000 W 0x0000_0000 14.4.2.13/14-40 _0000_0000 Chapter 4, “Reset, Clocking, Freescale Semiconductor for details. for for for ...

Page 135

... Refer to the MPC8313E Integrated Processor Hardware Specifications for a pinout diagram showing pin numbers and a listing of all the electrical and mechanical specifications. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor NOTE • Enhanced local bus interface signals • ...

Page 136

... LGPL2/LOE/LFRE IIC1_SCL/CKSTOP_IN 1 1 LGPL3/LFWP IIC2_SCL/GPIO[11 LGPL4/LGTA/LUPWAIT/LFRB 1 LGPL5 1 LCLK[0:1] 2 LA[0:4]/MSRCID[0:4]/GPIO[0:4] 5 LA[5]/MDVAL/GPIO[5] 1 LA[6:7]/GPIO[6:7] 2 LA[8:9]/GPIO[13:14] 2 LA[10:15] 6 eTSEC1 Ethernet and USB Interface 17 Signals eTSEC2 Ethernet Interface 17 Signals Ethernet Mgmt Interface 2 Signals Gigabit Reference Clock Interface 1 Signal Enhanced Local Bus Interface 58 Signals Freescale Semiconductor ...

Page 137

... Finally, the table provides a pointer to the table where the signal function is described. Table 3-1. MPC8313E Signal Reference by Functional Block Name Description MDQ[0:31] DDR data MDM[0:3] DDR data mask MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor USB_DP 1 1 USB_DM 1 1 USB_VBUS 1 2 ...

Page 138

... PCI 1 I/O 13-3/13-5 PCI 1 I/O 13-3/13-5 PCI 1 I 13-3/13-5 PCI 1 I 13-3/13-5 PCI 1 I/O 13-3/13-5 PCI 1 O 13-3/13-5 Alternate Function(s) — — — — — — — — — — — — — — — — — — — — — — — — CPCI_HS_ES — — CPCI_HS_LED Freescale Semiconductor ...

Page 139

... DUART ready to send 2 IIC1_SDA I C serial data 2 IIC1_SCL I C serial clock 2 IIC2_SDA I C serial data 2 IIC2_SCL I C serial clock MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Functional No. of Table/ I/O Block Signals Page PCI 1 O 13-3/13-5 PCI 1 I 13-3/13-5 PCI 1 O ...

Page 140

... O 15-2/15-8 eTSEC1 1 O 15-2/15-8 eTSEC1 1 O 15-2/15-8 eTSEC1 1 O 15-2/15-8 eTSEC1 1 O 15-2/15-8 Alternate Function(s) GTM1_TIN3/ GTM2_TIN4/LSRCID4 /GPIO28 GTM1_TGATE3/ GTM2_TGATE4/ LDVAL/GPIO29 GTM1_TOUT3/ GPIO30 GPIO31 USBDR_TXDRXD0 USBDR_TXDRXD1 USBDR_TXDRXD2 USBDR_TXDRXD3 USBDR_TXDRXD4 USBDR_TXDRXD [5:7] USBDR_NXT USBDR_DIR/ TSEC_1588_TRIG2 TSEC_1588_ALARM2 USBDR_CLK/ TSEC_1588_CLK TSEC_1588_GCLK TSEC_1588_PP1 TSEC_1588_PP2 USBDR_STP/ TSEC_1588_PP3 — Freescale Semiconductor ...

Page 141

... TSEC_MDIO Ethernet management data in/out TSEC_1588_CLK 1588 external timer reference clock input TSEC_1588_GCLK 1588 timers TSEC_1588_PP1 1588 timer pulse per period 1 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Functional No. of Table/ I/O Block Signals Page eTSEC2 1 I/O 15-2/15-8 eTSEC2 ...

Page 142

... I 15-2/15-8 SGMII PHY 1 I 15-2/15-8 2 SGMII PHY 1 I/O 15-2/15-8 SGMII PHY 1 I/O 15-2/15-8 3 SGMII PHY 1 I 15-2/15-8 3 SGMII PHY 1 I 15-2/15-8 SGMII PHY 1 O 15-2/15-8 SGMII PHY 1 O 15-2/15-8 Alternate Function(s) UART_RTS2/LA13 GPIO14/LA9 IIC1_SDA/LA14 LA7 LA8 IIC1_SCL/LA15 — — — — — — — — — — Freescale Semiconductor ...

Page 143

... LBC port address LA9 LBC port address LA10 LBC port address LA11 LBC port address LA12 LBC port address LA13 eLBC port address MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Functional No. of Table/ I/O Block Signals Page SGMII PHY 1 I 15-2/15-8 ...

Page 144

... O 10-2/10-5 eLBC 1 O 10-2/10-5 eLBC 1 O 10-2/10-5 eLBC 1 O 10-2/10-5 eLBC 1 O 10-2/10-5 eLBC 1 I/O 10-2/10-5 eLBC 1 O 10-2/10-5 eLBC 2 O 10-2/10-5 eLBC 1 1 — USB 1 I/O 16-1/16-3 Alternate Function(s) TSEC_1588_TRIG1 TSEC_1588_ALARM2 — — — — M1LALE — — — — — — — TSEC_MDC GTM1_TIN1/ GTM2_TIN2/ LSRCID0 Freescale Semiconductor ...

Page 145

... USB PLL USB_PLL_PWR3 Dedicated 3.3 V analog power for USB PLL USB_PLL_GND Dedicated analog ground for USB PLL USB_VSSA_BIAS Dedicated power for USB bias circuit MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Functional No. of I/O Block Signals USB 1 I/O USB 1 O ...

Page 146

... JTAG 1 O 20-2/20-2 JTAG 1 I 20-2/20-2 Alternate Function(s) — GPIO28/LSRCID4 SPIMOSI LDVAL/GPIO29/ SPIMISO GPIO15/TSEC2_COL GPIO16/TSEC2_CRS GPIO30/SPICLK GPIO17/ TSEC2_GTX_CLK GPIO18/ TSEC2_Rx_CLK GPIO19/ TSEC2_RX_DV GPIO24/ TSEC2_RX_ER LSRCID0/USBDR_ DRIVE_VBUS LSRCID1/USBDR_ PWRFAULT LSRCID2/ USBDR_PCTL0 — — — — CKSTOP_OUT CKSTOP_IN/ GPIO12 — — — — Freescale Semiconductor ...

Page 147

... GPIO15 General-purpose I/O signal 15 GPIO16 General-purpose I/O signal 16 GPIO17 General-purpose I/O signal 17 GPIO18 General-purpose I/O signal 18 GPIO19 General-purpose I/O signal 19 GPIO[20:23] General-purpose I/O signal 20-23 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Functional No. of Table/ I/O Block Signals Page JTAG 1 I 20-2/20-2 GPIO 5 I/O — GPIO 1 I/O — ...

Page 148

... Reset and 1 I/O 4-3/4-5 clock Reset and 1 I/O 4-3/4-5 clock Reset and 1 I 3-3/3-29 clock Alternate Function(s) GTM1_TOUT2/ GTM2_TOUT1/ TSEC2_RX_ER TSEC2_TX_CLK TSEC2_TX_EN TSEC2_TX_ER GTM1_TIN3/ GTM2_TIN4/ LSRCID4/SPIMOSI GTM1_TGATE3/ GTM2_TGATE4/ LDVAL/SPIMSO GTM1_TOUT3/ SPICLK SPISEL — — — IIC2_SDA/GPIO10 — — — — IIC1_SDA/ TSEC_1588_TRIG1 IIC1_SCL/ TSEC_1588_ALARM2 — Freescale Semiconductor ...

Page 149

... Memory debug data valid MDVAL Memory debug data valid LSRCID0 Memory debug source ID 0 LSRCID1 Memory debug source ID 1 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Functional No. of Table/ I/O Block Signals Page Reset and 1 I 3-6/3-31 clock ...

Page 150

... Reset and 1 I/O 4-3/4-5 clock Reset and 1 I/O 4-3/4-5 clock PCI 1 O 13-3/13-5 PCI 1 I 13-3/13-5 PCI 1 O 13-3/13-5 PMC 1 O 5-65/5-66 Alternate Function(s) GTM1_TOUT1/ USBDR_PCTL0 LBC_PM_REF_10/ USBDR_PCTL1 GTM1_TIN3/ GTM2_TIN4/ GPIO28/SPIMOSI GTM1_TGATE3/ GTM2_TGATE4/ GPIO29/SPIMISO Alternate Function(s) — — IIC1_SCL/ TSEC_1588_ALARM2 IIC1_SDA/ TSEC_1588_TRIG1 PCI_GNT2 PCI_REQ1 PCI_GNT1 — Freescale Semiconductor ...

Page 151

... GPIO19 General-purpose I/O signal 19 GPIO24 General-purpose I/O signal 24 GPIO25 General-purpose I/O signal 25 GPIO26 General-purpose I/O signal 26 GPIO27 General-purpose I/O signal 27 GPIO28 General-purpose I/O signal 28 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Functional No. of Table/ I/O Block Signals Page GPIO 5 I/O — GPIO 1 I/O — GPIO 1 I/O — ...

Page 152

... Global 1 I/O 5-54/5-52 Timers Global 1 I/O 5-54/5-52 Timers Alternate Function(s) GTM1_TGATE3/ GTM2_TGATE4/ LDVAL/SPIMSO GTM1_TOUT3/ SPICLK SPISEL LA5/MDVAL LA6 LA7/ TSEC_1588_TRIG2 UART_CTS1/ MSRCID2 UART_RTS1/ MSRCID3 LSRCID1/USBDR_ PWRFAULT GPIO19/ TSEC2_RX_DV LDVAL/GPIO29/ SPIMISO GPIO16/TSEC2_CRS LSRCID0/USBDR_ DRIVE_VBUS GPIO18/ TSEC2_Rx_CLK GPIO28/LSRCID4 SPIMOSI GPIO15/TSEC2_COL LSRCID2/ USBDR_PCTL0 GPIO24/ TSEC2_RX_ER GPIO30/SPICLK Freescale Semiconductor ...

Page 153

... LA6 LBC port address LA7 LBC port address LA8 LBC port address LA9 LBC port address LAD[0:15] LBC address/data MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Functional No. of Table/ I/O Block Signals Page Global 1 I/O 5-54/5-52 ...

Page 154

... O 10-2/10-5 eLBC 1 O 10-2/10-5 eLBC 1 O 10-2/10-5 eLBC 1 I/O 10-2/10-5 eLBC 1 O 10-2/10-5 Debug 1 I/O 10-2/10-5 Debug 1 I/O 10-2/10-5 Debug 1 I/O 10-2/10-5 Debug 1 I/O 10-2/10-5 Alternate Function(s) M1LALE TSEC_MDC — — — GTM1_TGATE3/ GTM2_TGATE4/ GPIO29/SPIMISO — — — — — — GTM1_TIN1/ GTM2_TIN2/USBDR _DRIVE_VBUS GTM1_TGATE1/ GTM2_TGATE2/ USBDR_DRIVE_ VBUS GTM1_TOUT1/ USBDR_PCTL0 LBC_PM_REF_10/ USBDR_PCTL1 Freescale Semiconductor ...

Page 155

... MODT[0:1] DRAM on-die termination MRAS DDR row address strobe MSRCID[0:4] Memory debug source ID 0–4 MSRCID0 Memory debug source ID 0 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Functional No. of Table/ I/O Block Signals Page Debug 1 I/O 10-2/10-5 eLBC 1 ...

Page 156

... PCI 1 I/O 13-3/13-5 PCI 1 I 13-3/13-5 PCI 1 I 13-3/13-5 PCI 1 O 13-3/13-5 PCI 1 I/O 13-3/13-5 PCI 1 I/O 13-3/13-5 Alternate Function(s) UARTSIN1 UART_CTS1/GPIO8 UART_RTS1/GPIO9 UART_SOUT2/ TSEC_1588_CLK — — — — — — — — — CPCI_HS_LED CPCI_HS_ENUM — — — — — — — CPCI_HS_ES — — — — Freescale Semiconductor ...

Page 157

... SD_REF_CLK SerDes PLL reference clock (complement) SDAVDD Analog supply for SerDes PLL SDAVSS Analog ground for SerDes PLL MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Functional No. of Table/ I/O Block Signals Page Clocks 1 I 4-2/4-3 Clocks ...

Page 158

... O 15-2/15-8 eTSEC 1 O 15-2/15-8 eTSEC 1 I 15-2/15-8 eTSEC 1 O 15-2/15-8 eTSEC 1 O 15-2/15-8 eTSEC 1 O 15-2/15-8 Alternate Function(s) GTM1_TOUT3/ GPIO30 GTM1_TGATE3/ GTM2_TGATE4/ LDVAL/GPIO29 GTM1_TIN3/ GTM2_TIN4/LSRCID4 /GPIO28 GPIO31 — — — — — — — — — — — LA8 IIC1_SCL/LA15 UART_SOUT2/LA10 UART_SIN2/LA11 UART_CTS2/LA12 UART_RTS2/LA13 Freescale Semiconductor ...

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... TSEC1_TX_CLK eTSEC1 transmit clock in TSEC1_TX_EN eTSEC1 transmit enable TSEC1_TX_ER eTSEC1 transmit error TSEC1_TXD0 eTSEC1 transmit data 2 TSEC1_TXD1 eTSEC1 transmit data 2 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Functional No. of Table/ I/O Block Signals Page eTSEC 1 O 15-2/15-8 eTSEC 1 I 15-2/15-8 ...

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... SGMII PHY 1 O 15-2/15-8 SGMII PHY 1 O 15-2/15-8 SGMII PHY 1 O 15-2/15-8 Alternate Function(s) TSEC_1588_PP1 TSEC_1588_GCLK GTM1_TIN4/ GTM2_TIN3/ GPIO15 GTM1_TGATE4/ GTM2_TGATE3/ GPIO16 GTM1_TOUT4/ GTM2_TOUT3/ GPIO17 GTM1_TIN2/ GTM2_TIN1/GPIO18 GTM1_TGATE2/ GTM2_TGATE1/ GPIO19 GTM1_TOUT2/ GTM2_TOUT1/ GPIO24 GPIO[20:23] GPIO25 GPIO26 GPIO27 CFG_RESET_ SOURCE[0:3] — — — — Freescale Semiconductor ...

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... USB_TPA Dedicated analog test signal USB_VBUS USB 2.0 VBUS line USB_VDDA Dedicated power for USB transceiver USB_VDDA_BIAS Dedicated ground for USB bias circuit MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Functional No. of I/O Block Signals DUART 1 I/O DUART 1 I/O DUART ...

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... PWR 15-2/15-8 SGMII PHY 3 GND 15-2/15-8 2 SGMII PHY 2 PWR 15-2/15-8 SGMII PHY 2 GND 15-2/15-8 Alternate Function(s) — — TSEC1_TX_CLK TSEC1_RX_ER GTM1_TIN1/ GTM2_TIN2/ LSRCID0 TSEC1_RXD0 GTM1_TOUT1/ LSRCID2 LSRCID3/ LBC_PM_REF_10 GTM1_TGATE1/ GTM2_TGATE2/ LSRCID1 TSEC1_TXD0/ TSEC_1588_PP3 TSEC1_RXD[3:1] TSEC1_COL TSEC1_CRS TSEC1_GTX_CLK TSEC1_RX_CLK TSEC1_RX_DV — — — — Freescale Semiconductor ...

Page 163

... DDR clock enable MCK DDR differential clocks MCK DDR differential clocks MODT[0:1] DRAM on-die termination MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Table 3-3. Reset Configuration Signals Functional Signal Name Reset Configuration Name TSEC2_TXD[3:0] CFG_RESET_SOURCE[0:3] None (dedicated pin) CFG_CLKIN_DIV ...

Page 164

... All ‘Z’ All ‘Z’ ‘0’ All ‘Z’ ‘0’ ’Z’ All ‘Z’ ‘0’ ‘1’ ‘1’ ‘1’ All ‘0’ ’1’ ’0’ ‘Z’ ‘Z’ ‘1’ Active clock Z Freescale Semiconductor ...

Page 165

... Signal I/O CFG_LBIU_MUX_EN I (LA[0:15]/GPIO) Meaning Timing This signal should be connected to pull-up or pull-down on the board. The signal MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Table 3-5. Signals for Multiplexing Multiplexing is Controlled By CFG_LBIU_MUX_EN RCWH[PCIARB] SICRL/SICRH Description State Asserted—GPIO ports function according to the values in their configuration registers (this may be eLBC or non-eLBC functionality). Negated— ...

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... Signal Descriptions MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 3-32 Freescale Semiconductor ...

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... Requirements An open-drain signal. An external pull-up is required. Reset State Output, driven low during power-on and hard reset flows. High impedance after reset MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Section 4.3.2, “Reset Configuration Words,” Table 4-1. System Control Signals Description Negated— ...

Page 168

... Section 4.3.1.2, “SYS_CLK_IN Division.” supplied (PORESET flow), and it must be pulled high or low by external resistors as long as HRESET is asserted. signal must be in the high-impedance state. Refer to the hardware specifications for proper resistors values to pull reset configuration signals high or low. Source.” Freescale Semiconductor ...

Page 169

... Timing Assertion/Negation—See the hardware specifications for timing information. Requirements Should be tied low if unused, for example when the clock is provided through Reset State Always input. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor they are defined in detail in their respective chapters. Table 4-2. External Clock Signals Description provided through SYS_CR_CLK_IN ...

Page 170

... Software watchdog reset • System bus monitor reset • Checkstop reset MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 4-4 Description through USB_CR_CLK_IN or when derived from the system clock. In PCI agent mode, this signal is typically not used. memory-mapped register. Section 4.3.1.2, Freescale Semiconductor ...

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... A soft reset causes a reset exception to the e300 core but does not reset other device logic. Table 4-4 identifies the reset actions for each reset source. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Section 4.5.1.3, “Reset Status Register (RSR),” Table 4-3. Reset Causes Description ...

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... Reset Source External Hard Reset Software Watchdog Power-On Reset Bus Monitor Checkstop Software Hard Reset Yes No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No External Soft JTAG Reset Reset Yes Yes Yes No Yes Freescale Semiconductor ...

Page 173

... The PCI interface can now accept external requests, if enabled, and the boot vector fetch by the core can proceed, if enabled. The device is now in its ready state. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Section 17.4.5, “Boot Sequencer Mode.” Section 6.2.1, “Arbiter Configuration Register Reset, Clocking, and Initialization ...

Page 174

... MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 4-8 Start loading reset configuration words Figure 4-1. Power-On Reset Flow NOTE PLLs are locked (no external indication) End loading reset configuration words. Duration depends on source After the configuration Freescale Semiconductor ...

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... Refer to the hardware specifications for proper resistor values for pulling reset configuration signals high or low. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Stable clock Start loading reset configuration words Figure 4-2 ...

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... Hard-coded option 1. Reset configuration word is not loaded. Hard-coded option 2. Reset configuration word is not loaded. Hard-coded option 3. Reset configuration word is not loaded. Hard-coded option 4. Reset configuration word is not loaded. Reserved Reserved Reserved Section 4.5.2.1, “System PLL Mode 2 C #1) or uses hard-coded Meaning 2 C EEPROM. PCI_CLK/PCI_SYNC_IN is Freescale Semiconductor ...

Page 177

... Mode) Words (Host Mode MHz No 66 MHz MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Table 4-6. SYS_CLK_IN Division Description shows how the user should pull down or pull up the reset configuration PCI_CLK CFG_RESET_ Frequency SOURCE[0:3] (Agent Mode) ...

Page 178

... NAND Flash) for information on the reset configuration word source. Reset Sequence Duration in SYS_CLK_IN/ Duration PCI_CLK Cycles μ 30420/15210 456 s μ 106534 3196 s μ 106534 1598 s μ 213068/106534 3196 s μ 23024 345 s μ 45284 679 s Section 4.2.1.2, “Reset Actions.” Freescale Semiconductor ...

Page 179

... System PLL Configuration The system PLL ratio reset, shown in signal and the internal csb_clk of the device. csb_clk drives internal units and feeds the e300 core PLL. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor SPMF — ...

Page 180

... BOOTSEQ SWEN DIS TSEC2M csb_clk : (PCI_CLK x (PCI Agent Mode) Reserved Reserved always selects the Maximum SPMF Value (Decimal Access: Read/Write ROMLOC RLEXT — TLE LALE Freescale Semiconductor 14 15 — — — ...

Page 181

... Boot ROM interface location. This bit combined with bit RLEXT determines where the device boots from. See ROM Location,” MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Description Configuration,” for more information. Pin Function When ...

Page 182

... PCI host Table 4-12. PCI Host/Agent Configuration 0 The device acts as a PCI agent device. 1 The device acts as the host processor (default). NOTE Section 4.3.2.2.4, Table 4-15 for more Table 4-15 for more for more information. for more information. Section 13.3, “Memory Meaning Freescale Semiconductor ...

Page 183

... BOOTSEQ MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Table 4-13. Boot Memory Space Boot memory space is 8 Mbytes at 0x0000_0000 to 0x007F_FFFF. e300 core register MSR[IP] initial value is 0b0. The core, if enabled to boot, begins fetching boot code from address 0x0000_0100 and exceptions are vectored to the physical address of 0x000 n_nnnn ...

Page 184

... Section 5.2, “Local Memory Map Overview and Example.” Table 4-15, establishes the location of NAND Flash Mode (RLEXT = 01) Reserved Local bus NAND Flash—8-bit small page ROM Reserved Reserved Reserved Local bus NAND Flash—8-bit large page ROM Reserved Reserved Freescale Semiconductor ...

Page 185

... The function of these signals can be changed by writing to this register during system initialization. See (SICRH).” MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Table Table 4-16. eTSEC1 Mode Configuration Value (Binary) ...

Page 186

... The eTSEC2 controller operates in the SGMII protocol, using the on-chip PHY. 111 Reserved NOTE Table Table 4-18. e300 Core True Little-Endian Value (Binary) 0 Big-endian mode 1 True little-endian mode 4-17, selects the protocol used by the Meaning 4-18, selects whether the e300 core Meaning Freescale Semiconductor ...

Page 187

... Table 4-21. Local Bus Reset Configuration Words Data Structure EEPROM Address 0x00 0x04 0x08 0x0C MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Table 4-19, configures the timing of the local bus Table 4-19. LALE Configuration Value (Binary) 0 Normal LALE timing ...

Page 188

... NAND Flash, 8 bit, large page MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 4-22 EEPROM Data Bits [0:7] [8:15] RCWL[16:23] RCWL[24:31] RCWH[0:7] RCWH[8:15] RCWH[16:23] RCWH[24:31] Table 4-22. Meaning BR0[PS] BR0[MSEL [16:23] [24:31] Table OR0[SCY] OR0[PGS] 000 1111 NA 001 0010 0 001 0010 1 Freescale Semiconductor 4-22. ...

Page 189

... Low Register (RCWLR),” and MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 2 C EEPROM 2 C boot sequencer is activated while the rest ...

Page 190

... Reset configuration word low [24–31] BYTE_EN CONT (1111) (1) RCWHR ADDR[14–21] RCWHR ADDR[22–29] Reset configuration word high [0–7] Reset configuration word high [8–15] Reset configuration word high [16–23] Reset configuration word high [24–31 RCWLR ADDR[12–13] RCWHR ADDR[12–13] Freescale Semiconductor ...

Page 191

... Reset Configuration Load Fail Failure of reset configuration load by the I 2 structure bus problem reset configuration load failure occurs, due to preamble fail or any other MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor ...

Page 192

... Section 4.3.1.1, “Reset Configuration Word Table 4-23 and Table Section 13.3.3.24, “PCI 8 9–15 16–31 Res COREPLL Res — Core clock: — csb_clk ratio 0 0000100 16’b0 0 0000101 16’b0 0 0000011 16’b0 0 0000100 16’b0 0 0000100 16’b0 Freescale Semiconductor 4-24. ...

Page 193

... Table 4-25. Examples For Hard-Coded Reset Configuration Words Usage CFG_RESET_SOURCE[0:3] PCI_CLK (MHz) csb_clk (MHz) DDR controller clock (MHz) Core clock (MHz) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Field Values when 1001 1010 1100 0 PCI agent mode ...

Page 194

... If SYS_CLK_IN is used as the system clock, the SYS_CR_CLK_IN (crystal input) must be tied to quiet ground; otherwise, SYS_CLK_IN must be tied to quiet ground. Similarly, if USB_CLK_IN is used as the USB clock, USB_CR_CLK_IN (crystal input) must be tied to quiet ground; otherwise, USB_CLK_IN must be tied to quiet ground. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 4-28 Freescale Semiconductor ...

Page 195

... SD_REF_CLK 125-MHz source Figure 4-7. Clock Subsystem Block Diagram The primary clock input to this device is PCI_CLK. This clock is the reference to the system APLL. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor e300c3 core Core PLL to DDR memory csb_clk ...

Page 196

... The csb_clk serves as the clock input to the e300 core. A second PLL inside the core multiplies up the csb_clk frequency to create the internal clock for the core (core_clk). The system and core PLL multipliers MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 4-30 Freescale Semiconductor ...

Page 197

... This allows for a single crystal or clock input to supply both system and USB references. The USB reference clock can be provided with a divide from these inputs (see MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Table 4-26 specifies which units have a configurable clock Table 4-26 ...

Page 198

... Reset mode register (RMR) 0x0_0918 Reset protection register (RPR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 4-32 Section 5.5, “Real Time Clock Module (RTC).” Table 4-27. Register Access Reset Section/Page R 0x0000_0000 4.5.1.1/4-33 R 0x0000_0000 4.5.1.2/4-33 — — — — R/W 0x0000_0000 4.5.1.3/4-33 R/W 0x0000_0000 4.5.1.4/4-35 R/W 0x0000_0000 4.5.1.5/4-35 Freescale Semiconductor — — ...

Page 199

... RSTSRC Reset configuration word source. Reflects the value of CFG_RESET_SOURCE input signal during the reset flow. See has no effect. 4–14 — Reserved, should be cleared. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor Register Access — ...

Page 200

... HRS is cleared by writing a 1 (writing zero has no effect hard reset event. 1 Hard reset event. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 4-34 Description 2 C boot sequencer has failed while loading the reset Freescale Semiconductor ...