MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 658

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Security Engine (SEC) 2.2
On occasion, a descriptor field may not be applicable to the requested service. With seven pointer dwords,
it is possible that not all these dwords will be required to specify the input and output parameters. (Some
operations, for example, do not require context.) Where a particular dword is not used, all fields should be
set to 0.
Some descriptors involve more than seven parcels of input and output data. In these cases, it is necessary
to use one POINTER field to address a sequence of data parcels.
LENGTH and EXTENT fields normally specify the sizes of data parcels. In some cases, however, the
POINTER field is zero, and the LENGTH and/or EXTENT fields simply specify values to be written to
an EU.
The J bit in each pointer dword is used to enable the scatter/gather feature. If a data parcel to be read or
written by the SEC is in one contiguous block of memory locations, then the scatter/gather feature is not
needed. In this case the POINTER should be set to point directly at the first byte of the parcel, and the J bit
should be 0. On the other hand, if the data parcel is stored in several separate segments of memory, then
the scatter/gather capability is needed to assemble or distribute the complete parcel. In this case, the
POINTER should be set to point to a link tables, and the J bit should be 1. For link table format, see
Section 14.3.4, “Link Table Format.”
14.3.4
Link tables implement scatter/gather capability. For gather operations, a link table specifies a list of
memory segments that are to be concatenated in the process of assembling data parcels. For scatter
operations, a link table specifies a list of memory segments into which the output data should be written.
Scatter or gather of a data parcel may be specified by a single link table or by a chain of link tables that are
linked together with pointers.
The link table or chain of link tables accessed through some descriptor POINTER must specify enough
memory segments to hold all the data that will be accessed through that pointer. In most cases, only a single
data parcel is accessed through a given POINTER, and the chain of link tables specifies just that parcel. In
other cases, the descriptor POINTER is used multiple times to access a sequence of data parcels, and the
chain of link tables must supply data for the entire sequence. If a link table is used to access a sequence of
data parcels, the end of each parcel must also be at the end of a memory segment. In other words, a single
memory segment must not straddle two data parcels.
A link table may contain any number of long word entries. There are two kinds of entries—regular entries
and next entries. Each ‘regular entry’ specifies a memory segment by means of a 32-bit starting address
(SegAdr) and a 16-bit length (SegLen). A ‘next entry’ is used at the end of a link table to specify that the
list of memory segments is continued in another link table. In a next entry, the N bit is set, the SegAdr field
gives the address of the next link table, and the SEGLEN field must be 0. A chain of link tables may
contain any number of link tables.
Whether the list of memory segments is in a single link table or split into several link tables, the last entry
in the last link table is a regular entry with the R (return) bit set. The R bit signifies the end of link table
operations so that the channel returns to the descriptor for its next pointer (if any). A single link table entry
is shown in
14-16
Link Table Format
Figure
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
14-6.
Freescale Semiconductor