MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 742

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
15.5.3.1.3
Interrupt events cause bits in the IEVENT register to be set. Software may poll this register at any time to
check for pending interrupts. If an event occurs and its corresponding enable bit is set in the interrupt mask
register (IMASK), the event also causes a hardware interrupt at the PIC. A bit in the interrupt event register
is cleared by writing a 1 to that bit position. A write of 0 has no effect.
Each eTSEC can issue three kinds of hardware interrupt to the PIC:
Some of the error interrupts are independently counted in the MIB block counters. Software may choose
to mask off these interrupts because these errors are visible to network management through the MIB
counters.
15-24
1. Transmit data frame interrupts—Issued whenever bits TXB or TXF of IEVENT are set to 1 and
2. Receive data frame interrupts—Issued whenever bits RXB or RXF of IEVENT are set to 1 and
3. Error, diagnostic, and special interrupts—Issued whenever bits MAG, GTSC, GRSC, TXC, RXC,
either transmit interrupt coalescing is disabled or the interrupt coalescing thresholds have been met
for TXF. To negate this hardware interrupt, software must clear both TXB and TXF bits.
either receive interrupt coalescing is disabled or the interrupt coalescing thresholds have been met
for RXF. To negate this hardware interrupt, software must clear both RXB and RXF bits.
BABR, BABT, LC, CRL, FGPI, FIR, FIQ, DPE, PERR, EBERR, TXE, XFUN, BSY, MSRO,
MMRD, or MMRW of IEVENT are set to 1. Software must clear all of these bits to negate an
error/diagnostic/special hardware interrupt.
— Magic Packet reception event is: MAG
— Operational diagnostics are events on: GTSC, GRSC, TXC, and RXC
— Interrupts resulting from errors/problems detected in the network or transceiver are: BABR,
— Interrupts resulting from internal or combination errors are: FIR, FIQ, DPE, PERR, EBERR,
— Special function interrupts are: FGPI, MSRO, MMRD, and MMRW
BABT, LC, and CRL
TXE, XFUN, and BSY
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Interrupt Event Register (IEVENT)
Table 15-7. TSEC_ID2[TSEC_INT] Field Settings (continued)
14
15
0 Can be configured to run in Ethernet normal/full mode
1 Ethernet normal/full mode off
0 Can be configured to run in Ethernet reduced mode
1 Ethernet reduced mode off
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