MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 756

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
Table 15-16
15-38
Bits
0
1
2
THLT0 Transmit halt of ring 0. Set by the eTSEC if is no longer processing transmit frames from this TxBD ring, and
THLT1 Transmit halt of ring 1. Set by the eTSEC if is no longer processing transmit frames from this TxBD ring, and
THLT2 Transmit halt of ring 2. Set by the eTSEC if is no longer processing transmit frames from this TxBD ring, and
Name
describes the fields of the TSTAT register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
DMA from this ring is disabled. To re-start transmission from this TxBD ring, this bit must be cleared by writing
1 to it. This bit is set only on a general error condition (as in IEVENT[TXE]), regardless of TQUEUE[EN0], or
if no ready TxBDs can be fetched. DMACTRL[GTS] being set by the user does not cause this bit to be set.
Software should examine the halted queue's buffer descriptors for repeatable error conditions before taking it
out of the halt state. Failure to do so may cause an effective livelock, in which the error condition recurs and
halts all queues again.
Repeatable error conditions which cause halt include:
Bus error:
TxBD programming errors:
DMA from this ring is disabled. To re-start transmission from this TxBD ring, this bit must be cleared by writing
1 to it. This bit is set only on a general error condition (as in IEVENT[TXE]), regardless of TQUEUE[EN1], or
if no ready TxBDs can be fetched.DMACTRL[GTS] being set by the user does not cause this bit to be set.
Software should examine the halted queue's buffer descriptors for repeatable error conditions before taking it
out of the halt state. Failure to do so may cause an effective livelock, in which the error condition recurs and
halts all queues again.
Repeatable error conditions which cause halt include:
Bus error:
TxBD programming errors:
DMA from this ring is disabled. To re-start transmission from this TxBD ring, this bit must be cleared by writing
1 to it. This bit is set only on a general error condition (as in IEVENT[TXE]), regardless of TQUEUE[EN2], or
if no ready TxBDs can be fetched. DMACTRL[GTS] being set by the user does not cause this bit to be set.
Software should examine the halted queue's buffer descriptors for repeatable error conditions before taking it
out of the halt state. Failure to do so may cause an effective livelock, in which the error condition recurs and
halts all queues again.
Repeatable error conditions which cause halt include:
Bus error:
TxBD programming errors:
• Invalid BD or data address
• Uncorrectable error on BD or data read
• Ready=1 and length=0
• Invalid BD or data address
• Uncorrectable error on BD or data read
• Ready=1 and length=0
• Invalid BD or data address
• Uncorrectable error on BD or data read
• Ready=1 and length=0
Table 15-16. TSTAT Field Descriptions
Description
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