MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 741

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 15-10
15.5.3.1.2
The controller ID register (TSEC_ID2) is a read-only register. The TSEC_ID2 register is used to identify
the eTSEC block configuration.
Table 15-6
Table 15-7
Freescale Semiconductor
16–23
24–31
0–15
Bits
10–15
16–23
24–31
Offset eTSEC1:0x2_4004; eTSEC2:0x2_5004
Reset 0
Bits
0–9
W
R
TSEC_REV_MN Value identifies the minor revision of the eTSEC.
TSEC_REV_MJ
0
describes the fields of the TSEC_ID2 register.
describes the field settings for TSEC_ID2[TSEC_INT].
TSEC_ID
describes the fields of the TSEC_ID register.
0
TSEC_CFG
Name
TSEC_INT
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Controller ID Register (TSEC_ID2)
0
Name
—
—
0
0
—
11–13
Value identifying the eTSEC (10/100/1000 Ethernet MAC).
0124 Unique identifier for eTSEC with 8 Rx and 8 Tx BD rings.
0800 Unique identifier for GMAC1 with 8 Rx and 8 Tx BD rings.
0810 Unique identifier for GMAC2 with 8 Rx and 8 Tx BD rings.
Value identifies the major revision of the eTSEC.
01 Silicon Rev 2.1
06 Silicon Rev 2.1
0
Bit
10
Reserved
Interface mode support. See
Reserved
Value identifies configuration options of the eTSEC.
00 eTSEC multiple ring, Rx TOE, Filer and Tx TOE supports are off
F0 eTSEC multiple ring, Rx TOE, Filer and Tx TOE supports are on
30 eTSEC multiple ring support is OFF and Rx TOE, Filer and Tx TOE supports are on
50 eTSEC multiple ring and filer supports are OFF and Rx TOE and Tx TOE supports are on
0
Table 15-7. TSEC_ID2[TSEC_INT] Field Settings
0
0 Ethernet mode not supported
1 Ethernet mode supported
Reserved
Table 15-6. TSEC_ID2 Field Descriptions
Table 15-5. TSEC_ID Field Descriptions
0
0
9
Figure 15-3. TSEC_ID2 Register
10
1
0
TSEC_INT
0
0
Table 15-7
0
15 16
0
Mode
0
Description
Description
for settings.
0
0
0
—
0
Enhanced Three-Speed Ethernet Controllers
0
0
23 24
0
1
1
1
TSEC_CFG
Access: Read only
1
0
0
0
15-23
31
0