MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 604

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

PCI Bus Interface
Table 13-16
13.3.2.10 PCI General Status Register (PCI_GSR)
PCI_GSR contains fields for providing status information, shown in
Table 13-17
13.3.2.11 PCI Inbound Translation Address Registers (PITAR n )
PITARn contains fields for defining the starting point of the inbound translation windows in the local
memory space (see
address translation registers, see
bus should not overlap. Therefore, situations where an inbound window translation points back into an
13-22
Offset 0x28
Reset
27–31
0–30
0–20
Bits
Bits
31
21
22
23
24
25
26
W
R
0
describes the bit settings of the PCI_ECR register.
PCISERR 0 An interrupt is generated if the corresponding bit of the PCI_ESR is 1.
shows the bit settings of the PCI_GSR register. All bits are read-only.
MPERR
NORSP
TPERR
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Name
Name
APAR
TABT
IDLE
—
—
—
Section 13.4.6, “PCI Inbound Address
Reserved
PCI controller is idle. Indicates when the PCI bus is totally idle before setting PCI_GCR[PPL].
0 The PCI controller is active.
1 The PCI controller is idle.
Reserved
1 A machine check is generated if the corresponding bit of the PCI_ESR is 1.
1 A machine check is generated if the corresponding bit of the PCI_ESR is 1.
1 A machine check is generated if the corresponding bit of the PCI_ESR is 1.
1 A machine check is generated if the corresponding bit of the PCI_ESR is 1.
1 A machine check is generated if the corresponding bit of the PCI_ESR is 1.
1 A machine check is generated if the corresponding bit of the PCI_ESR is 1.
Reserved
0 An interrupt is generated if the corresponding bit of the PCI_ESR is 1.
0 An interrupt is generated if the corresponding bit of the PCI_ESR is 1.
0 An interrupt is generated if the corresponding bit of the PCI_ESR is 1.
0 An interrupt is generated if the corresponding bit of the PCI_ESR is 1.
0 An interrupt is generated if the corresponding bit of the PCI_ESR is 1.
Figure 13-14. PCI General Status Register (PCI_GSR)
Table 13-17. PCI_GSR Field Descriptions
Table 13-16. PCI_ECR Field Descriptions
Chapter 11,
“Sequencer”). Inbound and outbound windows for the same
—
All zeros
Translation”; for more information on outbound
Description
Description
Figure
13-14.
Freescale Semiconductor
Access: Read-only
30
IDLE
31