MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1020

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
If the PID Code indicates an IN, then any of following responses are expected:
If the PID Code indicates an OUT/SETUP, then any of following responses are expected:
16.6.12.2 Split Transaction Interrupt
Split-transaction Interrupt-IN/OUT endpoints are managed using the same data structures used for
high-speed interrupt endpoints. They both co-exist in the periodic schedule. Queue heads/qTDs offer the
set of features required for reliable data delivery, which is characteristic to interrupt transfer types. The
split-transaction protocol is managed completely within this defined functional transfer framework. For
example, for a high-speed endpoint, the host controller will visit a queue head, execute a high-speed
transaction (if criteria are met) and advance the transfer state (or not) depending on the results of the entire
transaction. For low- and full-speed endpoints, the details of the execution phase are different (that is, takes
more than one bus transaction to complete), but the remainder of the operational framework is intact.
16.6.12.2.1 Split Transaction Scheduling Mechanisms for Interrupt
Full- and low-speed Interrupt queue heads have an EPS field indicating full- or low-speed and have a
non-zero S-mask field. The host controller can detect this combination of parameters and assume the
endpoint is a periodic endpoint. Low- and full-speed interrupt queue heads require the use of the split
transaction protocol. The host controller sets the Endpoint Type (ET) field in the split token to indicate the
transaction is an interrupt. These transactions are managed through a transaction translator's periodic
pipeline. Software should not set these fields to indicate the queue head is an interrupt unless the queue
head is used in the periodic schedule.
System software manages the per/transaction translator periodic pipeline by budgeting and scheduling
exactly during which micro-frames the start-splits and complete-splits for each endpoint will occur. The
characteristics of the transaction translator are such that the high-speed transaction protocol must execute
during explicit micro-frames, or the data or response information in the pipeline is lost.
illustrates the general scheduling boundary conditions that are supported by the EHCI periodic schedule
and queue head data structure. The S and C
start-splits and complete splits (respectively).
16-92
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DATA0/1. On reception of data, the host controller ensures the PID matches the expected data
toggle and checks CRC. If the packet is good, the host controller advances the state of the transfer
(for example, moves the data pointer by the number of bytes received, decrements the
BytesToTransfer field by the number of bytes received, and toggles the dt bit). The host controller
then exits this state. The response and advancement of transfer may trigger other processing events,
such as retirement of the qTD and advancement of the queue.
If the data sequence PID does not match the expected, the data is ignored, the transfer state is not
advanced and this state is exited.
ACK. The target endpoint accepted the data, so the host controller must advance the state of the
transfer. The Current Offset field is incremented by Maximum Packet Length or Bytes to Transfer,
whichever is less. The Bytes To Transfer field is decremented by the same amount and the data
toggle bit (dt) is toggled. The host controller then exits this state.
Advancing the transfer state may cause other processing events such as retirement of the qTD and
advancement of the queue.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
n
labels indicate micro-frames where software can schedule
Freescale Semiconductor
Figure 16-53