MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 51

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

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Freescale Semiconductor
TMR_CNT_H Register Definition ................................................................................... 15-117
TMR_ADD Register Definition........................................................................................ 15-118
TMR_ACC Register Definition ........................................................................................ 15-118
TMR_PRSC Register Definition ...................................................................................... 15-119
TMROFF_H/L Register Definition .................................................................................. 15-119
TMR_ALARM1-2_H/L Register Definition .................................................................... 15-120
TMR_FIPERn Register Definition ................................................................................... 15-121
TMR_ETTS1-2_H/L Register Definition ......................................................................... 15-121
Control Register Definition............................................................................................... 15-124
Status Register Definition ................................................................................................. 15-125
AN Advertisement Register Definition............................................................................. 15-126
AN Link Partner Base Page Ability Register Definition .................................................. 15-128
AN Expansion Register Definition ................................................................................... 15-129
AN Next Page Transmit Register Definition .................................................................... 15-130
AN Link Partner Ability Next Page Register Definition .................................................. 15-130
Extended Status Register Definition ................................................................................. 15-131
Jitter Diagnostics Register Definition ............................................................................... 15-132
TBI Control Register Definition ....................................................................................... 15-133
eTSEC-MII Connection .................................................................................................... 15-135
eTSEC-RMII Connection ................................................................................................. 15-136
eTSEC-RGMII Connection............................................................................................... 15-137
eTSEC-RTBI Connection ................................................................................................. 15-138
Definition of Custom Preamble Sequence ........................................................................ 15-149
Definition of Received Preamble Sequence...................................................................... 15-149
Ethernet Address Recognition Flowchart ......................................................................... 15-151
Sample C Code for Computing eTSEC Hash Table Indices............................................. 15-153
Location of Frame Control Blocks for TOE Parameters .................................................. 15-161
Transmit Frame Control Block ......................................................................................... 15-161
Receive Frame Control Block........................................................................................... 15-163
Structure of the Receive Queue Filer Table ...................................................................... 15-168
1588 Timer Design Partition ............................................................................................. 15-179
Ethernet Sampling Points for 1588 ................................................................................... 15-180
PTP Packet Format............................................................................................................ 15-181
Buffer Format for Transmit timestamp Insertion .............................................................. 15-183
Transmit Frame Control Block ......................................................................................... 15-183
Example of eTSEC Memory Structure for BDs ............................................................... 15-186
Buffer Descriptor Ring...................................................................................................... 15-186
Transmit Buffer Descriptor ............................................................................................... 15-187
Mapping of TxBDs to a C Data Structure......................................................................... 15-187
Receive Buffer Descriptor................................................................................................. 15-190
Mapping of RxBDs to a C Data Structure ........................................................................ 15-191
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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