MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1059

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

As a result of entering the Address state, the device address register (DEVICEADDR) must be
programmed by the DCD.
Entry into the Configured indicates that all endpoints to be used in the operation of the device have been
properly initialized by programming the ENDPTCTRLn registers and initializing the associated queue
heads.
16.8.2.1
A bus reset is used by the host to initialize downstream devices. When a bus reset is detected, the USB_DR
controller will renegotiate its attachment speed, reset the device address to 0, and notify the DCD by
interrupt (assuming the USB reset interrupt enable bit, USBINTR[URE], is set). After a reset is received,
all endpoints (except endpoint 0) are disabled and any primed transactions will be canceled by the device
controller. The concept of priming will be clarified below, but the DCD must perform the following tasks
when a reset is received:
Clear all setup token semaphores by reading the ENDPTSETUPSTAT register and writing the same value
back to the ENDPTSETUPSTAT register.
Clear all the endpoint complete status bits by reading the ENDPTCOMPLETE register and writing the
same value back to the ENDPTCOMPLETE register.
Cancel all primed status by waiting until all bits in the ENDPTPRIME are 0 and then writing
0xFFFF_FFFF to ENDPTFLUSH.
Read the reset bit in the PORTSC register (PORTSC[PR]) and make sure that it is still active. A USB reset
will occur for a minimum of 3 ms and the DCD must reach this point in the reset cleanup before end of the
reset occurs, otherwise a hardware reset of the device controller is recommended (rare.)
Free all allocated dTDs because they will no longer be executed by the device controller. If this is the first
time the DCD is processing a USB reset event, then it is likely that no dTDs have been allocated.
At this time, the DCD may release control back to the OS because no further changes to the device
controller are permitted until a Port Change Detect is indicated.
After a Port Change Detect, the device has reached the default state and the DCD can read the PORTSC
to determine if the device is operating in FS or HS mode. At this time, the device controller has reached
normal operating mode and DCD can begin enumeration according to the USB Chapter 9, Device
Framework.
In some applications, it may not be possible to enable one or more pipes while in FS mode. Beyond the
data rate issue, there is no difference in DCD operation between FS and HS modes.
Freescale Semiconductor
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A hardware reset can be performed by writing a one to the USB_DR reset bit in (USBCMD[RST]).
Note that a hardware reset will cause the device to detach from the bus by clearing USBCMD[RS]
bit. Thus, the DCD must completely re-initialize the USB_DR after a hardware reset.
Bus Reset
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
The device DCD may use the FS/HS mode information to determine the
bandwidth mode of the device.
NOTE
Universal Serial Bus Interface
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