MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 284

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

System Configuration
For completeness,
supports. If the device is used as a PCI agent, the supported bus states are B0 and B1, since the PCI clock
is running in these two states. Otherwise, as a host, the device could be configured to support all the bus
states.
1
2
3
4
5
Below is a summary of the new PCI Power Management Interface Specification capabilities supported on
the device:
5-76
PCI Dx Power
B0 (full on)
Bus State
Requires the device to hold the PCI bus in idle state
The device cannot process wake-up events with the PCI bus in this state and the bus must be returned to B0 state through a
PORESET.
Requires the device to turn off PCI bus clock
The device cannot process wake-up events with the PCI bus in this state and the bus must be returned to B0 state through a
PORESET.
Requires the device to turn off the PCI bus clock through the output clock control register (OCCR), and to turn off the PCI bus
VDD through some customer-defined method (perhaps GPIO).
PCI Bx
•
•
•
•
D3Cold
D3Hot
B1
B2
B3
State
Generation of PCI_PME signal to an external PCI host when the device is operating in agent mode.
Responding to PCI_PME as an input wake-up event when the device is operating as PCI host.
Responding to other wake-up events from various sources: Ethernet Magic Packet, USB, GPIO,
internal timer, external interrupt, PCI PME# (PCI_PME).
Properly sequencing the device into and out its lowest power mode where VDD is removed to a
portion of the die.
PCI Bus
VDD
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
On
On
On
Off
Supported
Yes
Yes
Table 5-72. PCI Defined Power Management State Support (continued)
Table 5-73
*
PCI Bus
Clock
Yes
Yes
No
No
e300 in Sleep mode. In D3Hot VDD is still applied to the entire device. In this mode you have an
option to power-off a portion of the device VDD. This is referred to as D3Warm. In D3Warm,
power is removed to the e300, DDR, LBC and IPIC. Power is not removed to Ethernet, USB, PCI,
GPIO and timers. PME signaling is supported in either D3Hot or D3Warm.
*
similar to PCI D3Hot state but with a portion of the chip powered off.
According to PCI PM Specification 1.2, in D3Cold the PCI clock is removed and all devices will
be reset when power is restored. The device can be placed into D3Cold state, but wake-up events
cannot be recognized or generated and when power is restored, the device must go through a
normal power-on reset boot sequence as it needs to be re-initialized.
PME signaling is not supported in D3Cold. For PME signaling, use the D3Warm state, which is
Table 5-73. PCI Bus Power Management State Support
Any PCI transaction, function interrupt, or PME event
PME event; bus is idle
PME event
PME event
shows the PCI bus power management states (B0–B3) that the device
PCI Bus Activity
How Supported
No
Support in PCI
Agent Mode
No
4
(no bus clock
or VDD)
2
clock)
Yes
Yes
(no bus
Freescale Semiconductor
Support in PCI
Host Mode
Yes
Yes
Yes
Yes
1
3
5