MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 511

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

10.4.3.2.1
There are two kinds of command instruction:
The manufacturer’s datasheet should be consulted to determine values for programming into the FCR
register, and whether a given command in the sequence is expected to initiate busy device behavior.
Freescale Semiconductor
•
•
Commands that issue immediately—CM0, CM1, CM2, and CM3. These commands write a single
command byte by asserting LFCLE and LFWE while driving an 8-bit command onto LAD[0:7].
Op-code CMn sources its command byte from field FCR[CMDn], therefore up to four different
commands can be issued in any FCM instruction sequence.
Commands that wait for LFRB to be sampled high (EEPROM in ready state) before
issuing—CW0, and CW1. These commands first poll the LFRB pin, waiting for it to go high,
before writing a single command byte onto LAD[0:7], sourced from FCR[CMDn] for op-code
CWn. It is necessary to use CWn op-codes whenever the EEPROM is expected to be in a busy state
(such as following a page read, block erase, or program operation) and therefore initially
unresponsive to commands. To avoid deadlock in cases where the device is already available, FCM
does not expect a transition on LFRB. Rather, FCM waits for 8×(2+ORn[SCY]) clock cycles
(when ORn[TRLX] = 0) or 16×(2+ORn[SCY]) clock cycles (when ORn[TRLX] = 1) before
sampling the level of LFRB. If the level of LFRB does not return high before a time-out set by
FMR[CWTO] occurs, FCM proceeds to issue the command normally, and a FCT event is issued
to LTESR.
FBAR Register
FBCR Register
FPAR Register
MDR Register
FMR Register
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
FCR Register
FCM Command Instructions
MDR AS select
Figure 10-50. FCM Instruction Sequencer Mechanism
OP0
FCM Instruction
Buffer
NAND Flash
Bus Signal
Generator
4 bits
op-code
4 bits
OP1
data
8 bits
OP2
Flash instruction shift register
OP3
FIR Register
LAD[0:7]
LFWE
LFCLE
LFALE
LFRE
LFRB
LFWP
parallel load on FCM bank select
OP4
OP5
OP6
Enhanced Local Bus Controller
OP7
NOP
10-63