MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 454

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
10-6
LGTA/LGPL4/
LOE/LGPL2/
LUPWAIT
LGPL0/
LGPL1/
LGPL3/
LFWE/
LFCLE
LGPL5
Signal
LWE0/
LWE1/
LFALE
LFWP
LFRB/
LBS0,
LFRE
LBS1
Table 10-2. Enhanced Local Bus Controller Detailed Signal Descriptions (continued)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
I/O
I/O GPCM transfer acknowledge/General-purpose line 4/FCM Flash ready-busy/UPM wait.
O
O
O
O
O
O
GPCM write enable 0/FCM write enable/UPM byte select 0. These signals select or validate each byte
lane of the data bus. For an 8-bit port size, bit 0 is the only defined signal. The least-significant address
bits of each access also determine which byte lanes are considered valid for a given data transfer.
General purpose line 0/FCM command latch enable.
General-purpose line 1/FCM address latch enable.
GPCM output enable/General-purpose line 2/FCM read enable.
General-purpose line 3/FCM write protect.
General-purpose line 5
Meaning
Meaning
Meaning
Meaning
Meaning
Meaning
Meaning
Timing Assertion/Negation—See
State
State
State
State
State
State
State
Asserted/Negated—For GPCM operation, LWE[0:1] assert for each byte lane enabled for
Asserted/Negated—In UPM mode, LGPL0 is one of six general purpose signals; it is driven
Asserted/Negated—In UPM mode, LGPL1 is one of six general purpose signals; it is driven
Asserted/Negated—Controls the output buffer of memory when accessing memory/devices in
Asserted/Negated—In UPM mode, LGPL3 is one of six general purpose signals; it is driven
Asserted/Negated—Input in GPCM or FCM modes used for transaction termination. It may
Asserted/Negated—One of six general purpose signals when in UPM mode, and drives a
writing.
LFWE enables command, address, and data writes to NAND Flash EEPROMs controlled
by FCM.
LBS[0:1] are programmable byte-select signals in UPM mode. See
“RAM
for details regarding the timing of LWE[0:1].
with a value programmed into the UPM array.
In FCM mode, LFCLE enables command cycles to NAND Flash EEPROMs.
with a value programmed into the UPM array.
In FCM mode, LFALE enables address cycles to NAND Flash EPROMs.
GPCM mode.
In UPM mode, LGPL2 is one of six general purpose signals; it is driven with a value
programmed into the UPM array.
LFRE enables data read cycles from NAND Flash EEPROMs controlled by FCM.
with a value programmed into the UPM array.
In FCM mode LFWP protects NAND Flash EEPROMs from accidental erasure and
programming when LFWP is asserted low—see
Register
also be configured as one of six general-purpose output signals when in UPM mode or
as an input to force the UPM controller to wait for the memory/device. FCM uses LFRB
to stall during long-latency read and programming operations, continuing once LFRB
returns high.
value programmed in the UPM array.
Array,” for programming details about LBS[0:1].
(FMR),” for programming of FCM operations to control LFWP.
Section 10.4.2, “General-Purpose Chip-Select Machine
Description
Section 10.3.1.17, “Flash Mode
Freescale Semiconductor
Section 10.4.4.4,
(GPCM),”