MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 630

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

PCI Bus Interface
a configuration access is for a device on the PCI bus by decoding a configuration command. When in agent
mode, the PCI controller responds to host-generated PCI configuration cycles when its IDSEL is asserted
during a configuration cycle.
For memory accesses, the address is decoded using AD[31:2]; thereafter, the address is incremented
internally by 4 bytes until the end of the burst transfer. Another initiator in a memory access should drive
0b00 on AD[1:0] during the address phase to indicate a linear incrementing burst order. The PCI controller
checks AD[1:0] during a memory command access and provides the linear incrementing burst order. On
reads, if AD[1:0] is 0b10, which represents a cache line wrap, the PCI controller linearly increments the
burst order starting at the critical 64-bit address, wraps at the end of the cache line, and disconnects after
reading one cache line. If AD[1:0] is 0bx1 (a reserved encoding) and the PCI_C/BE[3:0] signals indicate
a memory transaction, it executes a target disconnect after the first data phase is completed. Note that
AD[1:0] are included in parity calculations.
13.4.3.3
As a target, the PCI controller drives PCI_DEVSEL one clock following the address phase as indicated in
the configuration space status register; see
information. The PCI controller as a target qualifies the address/data lines with PCI_FRAME before
asserting PCI_DEVSEL. The PCI_DEVSEL signal is asserted at or before the clock edge at which the PCI
controller enables its PCI_TRDY, PCI_STOP, or data (for a read). The PCI_DEVSEL signal is not negated
until PCI_FRAME is negated, with PCI_IRDY asserted and either PCI_STOP or PCI_TRDY asserted.
The exception to this is a target-abort; see
information.
As an initiator, if the PCI controller does not see the assertion of PCI_DEVSEL within 4 clocks of
PCI_FRAME, it terminates the transaction with a master-abort as described in
“Transaction Termination,”
13.4.3.4
The byte enable signals (BE[3:0]) indicate which byte lanes carry valid data. The byte enable signals may
enable different bytes for each of the data phases. The byte enable signals are valid on the edge of the clock
that starts each data phase and remain valid for the entire data phase.
If the PCI controller, as a target, sees no byte enable signals asserted, it completes the current data phase
with no permanent change. This implies that on a read transaction, the PCI controller expects the data not
to be changed, and on a write transaction, the data is not stored.
13.4.3.5
The turnaround-cycle is one clock cycle and is required to avoid contention. This cycle occurs at different
times for different signals. PCI_IRDY, PCI_TRDY, and PCI_DEVSEL use the address phase as their
turnaround-cycle. PCI_FRAME, PCI_C/BE[3:0], and AD[31:0] use the idle cycle between transactions as
their turnaround-cycle. (An idle cycle in PCI is when both PCI_FRAME and PCI_IRDY are negated).
Byte lanes not involved in the current data transfer are driven to a stable condition even though the data is
not valid.
13-48
Device Selection
Byte Enable Signals
Bus Driving and Turnaround
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
for more information.
Section 13.3.3.4, “PCI Status Configuration Register,”
Section 13.4.3.8, “Transaction Termination,”
Section 13.4.3.8,
Freescale Semiconductor
for more
for more