MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 743

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Figure 15-4
Table 15-8
Freescale Semiconductor
Offset eTSEC1:0x2_4010; eTSEC2: 0x2_5010
Reset
Reset
Bits
0
1
2
3
4
5
6
W
W
R BABR
R
RXB
w1c
w1c
16
0
EBERR Internal bus error. This bit indicates that a system bus error occurred while a DMA transaction was
MSRO
Name
BABR
GTSC
RXC
BSY
—
describes the fields of the IEVENT register.
describes the definition for the IEVENT register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
RXC
w1c
17
1
maximum frame length register while MACCFG2[Huge Frame] is set.
0 Excessive frame not received.
1 Excessive frame received.
Receive control interrupt. A control frame was received while MACCFG1[Rx_Flow] is set. As soon as the
transmitter finishes sending the current frame, a pause operation is performed.
0 Control frame not received.
1 Control frame received.
0 No frame received and discarded.
1 Frame received and discarded.
underway. As a result, transferred data is expected to be partially or completely invalid.
0 No system bus error occurred.
1 System bus error occurred.
Reserved
size of its register.
0 MIB count not exceeding its register size.
1 MIB count exceeds its register size.
the transmitter is put into a pause state after completion of the frame currently being transmitted.
0 No graceful stop interrupt.
1 Graceful stop requested.
Babbling receive error. This bit indicates that a frame was received with length in excess of the MAC’s
Busy condition interrupt. Indicates that a frame was received and discarded due to a lack of buffers.
MIB counter overflow. This interrupt is asserted if the count for one of the MIB counters has exceeded the
Graceful transmit stop complete. This interrupt is asserted for one of two reasons. Graceful stop means that
• A graceful stop, which was initiated by setting DMACTRL[GTS], is now complete.
• A transmission of a flow control PAUSE frame, which was initiated by setting TCTRL[TFC_PAUSE], is
now complete.
BSY
w1c
2
—
EBERR
w1c
19
3
Figure 15-4. IEVENT Register Definition
Table 15-8. IEVENT Field Descriptions
MAG MMRD MMWR GRSC RXF
w1c
—
20
4
MSRO
w1c
w1c
21
5
GTSC
w1c
w1c
All zeros
All zeros
22
6
Description
BABT TXC TXE TXB TXF
w1c
w1c
23
7
w1c
w1c
24
8
Enhanced Three-Speed Ethernet Controllers
w1c
25
9
—
w1c w1c
10
26
FGP
w1c w1c w1c w1c
11
27
I
FIR FIQ DPE PERR
—
12
28
w1c w1c
LC CRL XFUN
13
29
Access: w1c
14
30
w1c
w1c
15-25
15
31