MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 397

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

9.2.1
The DDR memory controller supports the following modes:
9.3
This section provides descriptions of the DDR memory controller’s external signals. It describes each
signal’s behavior when the signal is asserted or negated and when the signal is an input or an output.
9.3.1
Memory controller signals are grouped as follows:
Table 9-1
specification has a pinout diagram showing pin numbers. It also lists all electrical and mechanical
specifications.
Freescale Semiconductor
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MDQS[0:3]
MDQ[0:31]
MCS[0:1]
MA[14:0]
MBA[2:0]
MCAS
MRAS
Name
MWE
Support for up to eight posted refreshes
Memory controller clock frequency of two times the SDRAM clock with support for sleep power
management
32-byte cache line wrap mode
Dynamic power management mode. The DDR memory controller can reduce power consumption
by negating the SDRAM CKE signal when no transactions are pending to the SDRAM.
Auto-precharge mode. Clearing DDR_SDRAM_INTERVAL[BSTOPRE] causes the memory
controller to issue an auto-precharge command with every read or write transaction.
Auto-precharge mode can be enabled for separate chip selects by setting
CSn_CONFIG[AP_n_EN].
Memory interface signals
Clock signals
Debug signals
External Signal Descriptions
shows how DDR memory controller external signals are grouped. The device hardware
Modes of Operation
Signals Overview
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Data bus
Data strobes
Column address strobe
Address bus
Logical bank address
Chip selects
Write enable
Row address strobe
Table 9-1. DDR Memory Interface Signal Summary
Function/Description
All zeros
All zeros
All zeros
All zeros
All ones
Reset
One
One
One
DDR Memory Controller
Pins
32
15
4
1
3
2
1
1
I/O
I/O
I/O
O
O
O
O
O
O
9-3