MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 376

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Integrated Programmable Interrupt Controller (IPIC)
8.5.8
Each bit in the SEPNR, shown in
interrupt is received, the interrupt controller sets the corresponding SEPNR bit.
Table 8-16
8.5.9
The SMPRR_A, shown in
8-18
Offset 0x2C
Reset
Reset
5–31
Offset 0x30
Reset 0
Bits Name
0–4
W
W
W
R
R
R
1
2
IRQ0
IRQ n Each bit corresponds to an external interrupt source. When an external interrupt is received, the interrupt
0
MIXA0P
—
16
This bit is valid only if the IRQ0 signal is configured as an external maskable interrupt (SEMSR[SIRQ0] = 0)
The user should drive all IRQ inputs to an inactive state prior to reset negation
0
0
The reset values of implemented bits reflect the values of the external IRQ signals. Reserved bits are zeros.
1
defines the bit fields of SEPNR.
System External Interrupt Pending Register (SEPNR)
System Mixed Interrupt Group A Priority Register (SMPRR_A)
controller sets the corresponding SEPNR bit.
When a pending interrupt is handled, the user must clear the corresponding SEPNR bit. For level triggered cases,
the software needs to cause the IRQn to negate which automatically clears the bit in SEPNR. For edge-triggered
cases, the software needs to clear the corresponding bit in SEPNR.
SEPNR bits are cleared by writing ones to them. Because the user can only clear bits in this register, writing zeros
to this register has no effect.
Note that the SEPNR bit positions are not changed according to their relative priority.
Write ignored, read = 0
IRQ1 IRQ2 IRQ3 IRQ4
2
0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
1
Figure 8-12. System Mixed Interrupt Group A Priority Register (SMPRR_A)
3
0
MIXA1P
0
Figure 8-11. System External Interrupt Pending Register (SEPNR)
2
1
5
0
6
MIXA2P
Figure
3
1
0
8
4
Figure
Table 8-16. SEPNR Field Descriptions
8-12, defines the priority among the sources listed in
0
9
MIXA3P
1
5
11 12
8-11, corresponds to an external interrupt source. When an
1
0
0
—
0
All zeros
15 16
Description
0
—
1
MIXA4P
0
18 19
0
1
MIXA5P
0
—
21 22
1
1
MIXA6P
1
24 25
0
Freescale Semiconductor
1
MIXA7P
Table
1
Access: Read/write
Access: Read/write
27 28
1
8-17.
0
0
—
2
0
15
31
31
0