MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1138

Manufacturer Part Number

MPC8313ZQADDC

Microprocessors - MPU 8313 REV2.2 PB NO ENC

Manufacturer

Freescale Semiconductor

Processor Series

Data Bus Width

Maximum Clock Frequency

Program Memory Size

Data Ram Size

Interface Type

Mounting Style

Package / Case

Number Of Programmable I/os

Number Of Timers

Manufacturer

BOSTOCK HK LIMITED

Part Number:

MPC8313ZQADDC

Manufacturer:

Freescale Semiconductor

Serial Peripheral Interface

The maximum sustained data rate that the SPI supports is input clock/50. However, the SPI can transfer a

single character at much higher rates—input clock/4 in master mode and input clock/2 in slave mode. Gaps

should be inserted between multiple characters to keep from exceeding the maximum sustained data rate.

The SPI’s four wire interface consists of transmit, receive, clock, and slave select.

External Signal Descriptions

MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2

All signals are open-drain.

For a multiple-master configuration with more than two masters, SPISEL and SPIE[MME]

do not detect all possible conflicts.

It is the responsibility of software to arbitrate for the SPI bus (with token passing, for example).

SELOUT x signals are implemented in software with general-purpose I/O signals.

Figure 19-3. Multiple-Master Configuration

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