MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 127

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
0x2_45C0–
0x2_45AC
0x2_45BC
0x2_457C
0x2_458C
0x2_459C
0x2_45A0
0x2_45A4
0x2_45A8
0x2_45B0
0x2_45B4
0x2_45B8
0x2_467C
0x2_468C
0x2_469C
0x2_4570
0x2_4574
0x2_4578
0x2_4580
0x2_4584
0x2_4588
0x2_4590
0x2_4594
0x2_4598
0x2_4680
0x2_4684
0x2_4688
0x2_4690
0x2_4694
0x2_4698
Offset
MAC06ADDR1*—MAC exact match address 6, part 1
MAC06ADDR2*—MAC exact match address 6, part 2
MAC07ADDR1*—MAC exact match address 7, part 1
MAC07ADDR2*—MAC exact match address 7, part 2
MAC08ADDR1*—MAC exact match address 8, part 1
MAC08ADDR2*—MAC exact match address 8, part 2
MAC09ADDR1*—MAC exact match address 9, part 1
MAC09ADDR2*—MAC exact match address 9, part 2
MAC10ADDR1*—MAC exact match address 10, part 1
MAC10ADDR2*—MAC exact match address 10, part 2
MAC11ADDR1*—MAC exact match address 11, part 1
MAC11ADDR2*—MAC exact match address 11, part 2
MAC12ADDR1*—MAC exact match address 12, part 1
MAC12ADDR2*—MAC exact match address 12, part 2
MAC13ADDR1*—MAC exact match address 13, part 1
MAC13ADDR2*—MAC exact match address 13, part 2
MAC14ADDR1*—MAC exact match address 14, part 1
MAC14ADDR2*—MAC exact match address 14, part 2
MAC15ADDR1*—MAC exact match address 15, part 1
MAC15ADDR2*—MAC exact match address 15, part 2
Reserved
TR64—Transmit and receive 64-byte frame counter
TR127—Transmit and receive 65- to 127-byte frame
counter
TR255—Transmit and receive 128- to 255-byte frame
counter
TR511—Transmit and receive 256- to 511-byte frame
counter
TR1K—Transmit and receive 512- to 1023-byte frame
counter
TRMAX—Transmit and receive 1024- to 1518-byte frame
counter
TRMGV—Transmit and receive 1519- to 1522-byte good
VLAN frame count
RBYT—Receive byte counter
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Register
Table 2-2. Memory Map (continued)
eTSEC Transmit and Receive Counters
eTSEC Receive Counters
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
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Section/Page
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Memory Map
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