MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 269

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 5-63
5.7.5.7
The global timers prescale registers (GTPSR1, GTPSR2, GTPSR3, and GTPSR4) are shown in
Figure
Erratic behavior may occur if GTPSRn is not initialized before the corresponding GTMDRn.
Table 5-64
Freescale Semiconductor
Offset
0–13
8–15
Bits
Bits
0–7
14
15
Reset
W
R
5-47.
Name
0x38(GTPSR1)
0x3A(GTPSR2)
Name
CAP
PPS
REF
—
—
0
0
defines the bit fields of GTEVRn.
defines the bit fields of GTPSRn.
Global Timers Prescale Registers (GTPSR1–GTPSR4)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
The total timer prescale value is calculated as follows:
This gives a total prescale range from 1 (GTPSRn[PPS] = 0x00,
GTMDRn[SPS] = 0x00) to 65,536 (GTPSRn[PPS] = 0xFF, GTMDR[SPS]
= 0xFF).
GTMn
Output reference event
0 No event
1 The counter reached the GTRFR n [TRV] value. GTMDR n [ORI] is used to enable the interrupt request
Counter capture event
Corresponding timer’s 16-bit read/write up-counter value.
0 No event
1 The counter value has been latched into the GTCPR n [LCV]. GTMDR n [CE] is used to enable generation
Reserved, should be cleared.
Primary prescaler bits
The primary prescaler is programmed to divide the clock input to corresponding timer by values from 1 to 256.
The value 0x00 divides the clock by 1 and 0xFF divides the clock by 256.
Reserved, should be cleared.
0
caused by this event.
of this event.
Figure 5-47. Global Timers Prescale Registers (GTPSR1–GTPSR4)
prescale r
0
0x3C(GTPSR3)
0x3E(GTPSR4)
=
0
(
—
GTPSRn PPS
0
Table 5-63. GTEVR n Bit Settings
Table 5-64. GTPSR n Bit Settings
[
0
]
+
0
1
)
NOTE
⋅
(
GTMDRn SPS
7
0
Description
Description
0
8
[
0
]
+
1
)
0
0
PPS
0
System Configuration
Access: Read/Write
0
1
5-61
15
1