MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 318

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Arbiter and Bus Monitor
See
(AIDR),” Section 6.2.5, “Arbiter Mask Register (AMR),” Section 6.2.6, “Arbiter Event Attributes
Register (AEATR),” Section 6.2.7, “Arbiter Event Address Register (AEADR),”
“Arbiter Event Response Register (AERR),”
6.4
The following sections describe the initialization and error handling sequences for the arbiter.
6.4.1
The following initialization sequence is recommended:
6.4.2
The following error handling sequence is recommended:
6-16
1. Write to ACR to configure pipeline depth, address bus parking mode, global maximum repeat
2. Write to AERR defines whether different error events cause a reset request or an interrupt.
3. Write to AIDR defines the kind of interrupt (regular or MCP) caused by each error event. Note that
4. Write to AMR to enable interrupts.
5. Write to ATR to set the ATO and DTO timers. Note that this is only necessary if the required timers
1. Read to AER to find out about the error that occurred in the system. Also, read the values of
2. If those registers are not accessible because of a bus deadlock situation, reset the chip and read the
3. Clear all the previous events by writing ones to the AER. This register is also cleared after reset.
Section 6.2.3, “Arbiter Event Register (AER),” Section 6.2.4, “Arbiter Interrupt Definition Register
count PCI maximum.
this is necessary only if interrupts are enabled and AERR defines error events to cause interrupt.
are less than the maximum value (which is default).
AEATR and AEADR to check on the first error event in the system.
values of the AEATR and AEADR registers to check on the event that causes this problem to the
system. Use HRESET to reset the chip to guarantee that the information stored in AEATR and
AEADR is not lost.
Initialization/Applications Information
Initialization Sequence
Error Handling Sequence
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
for more information.
and
Freescale Semiconductor
Section 6.2.8,