MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 413

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 9-12
Freescale Semiconductor
11–12
Bits
5–7
8–9
10
13
14
0
1
2
3
4
SDRAM_TYPE
DYN_PWR
MEM_EN
RD_EN
describes the DDR_SDRAM_CFG fields.
SREN
NCAP
Name
8_BE
DBW
—
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
0 SDRAM interface logic is disabled.
1 SDRAM interface logic is enabled. Must not be set until all other memory configuration
0 SDRAM self refresh is disabled during sleep. Whenever self-refresh is disabled, the system is
1 SDRAM self refresh is enabled during sleep.
Reserved. Must be cleared.
0 Indicates unbuffered DRAM modules.
1 Indicates registered DRAM modules.
Note: RD_EN and 2T_EN must not both be set at the same time.
Reserved
initialization sequence to DRAM through Mode Register Set and Extended Mode Register Set
commands. Default value is 010 designating DDR1 SDRAM.
000–001Reserved
010 DDR1 SDRAM
011 DDR2 SDRAM
100 Reserved
101 Reserved
110 Reserved
111 Reserved
Reserved
0 Dynamic power management mode is disabled.
1 Dynamic power management mode is enabled. If there is no ongoing memory activity, the
DRAM data bus width.
00
01
10
11
0 4-beat bursts are used on the DRAM interface.
1 8-beat bursts are used on the DRAM interface.
Note: DDR1 (SDRAM_TYPE = 010) must use 8-beat bursts when using 32-bit bus mode (32_BE =
precharge. If one of these devices is used, then this bit needs to be set if auto precharge is used.
0 DRAMs in system support concurrent auto-precharge.
1 DRAMs in system do not support concurrent auto-precharge.
DDR SDRAM interface logic enable.
Self refresh enable (during sleep).
Registered DRAM module enable. Specifies the type of DRAM module used in the system.
Type of SDRAM device to be used. This field is used when issuing the automatic hardware
Dynamic power management mode
8-beat burst enable.
Non-concurrent auto-precharge. Some older DDR DRAMs do not support concurrent auto
parameters have been appropriately configured by initialization code.
responsible for preserving the integrity of SDRAM during sleep.
SDRAM CKE signal is negated.
Reserved
32-bit bus is used
16-bit bus is used
Reserved
Table 9-12. DDR_SDRAM_CFG Field Descriptions
1) and 4-beat bursts when using 64-bit bus mode; DDR2 (SDRAM_TYPE = 011) must use
4-beat bursts, even when using 32-bit bus mode
Description
DDR Memory Controller
9-19