MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 498

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
The timing diagram in
LCRR[CLKDIV] = 4 or 8. If LCRR[CLKDIV] = 2, LCSn asserts identically for OR
10.4.2.3.1
The GPCM supports internal generation of transfer acknowledge. It allows between zero and 30 wait states
to be added to an access by programming OR
acknowledge is enabled if OR
before the wait state counter has expired (to allow for synchronization latency), the current memory cycle
is terminated by LGTA; otherwise it is terminated by the expiration of the wait state counter. Regardless
of the setting of OR
manner. When TRLX = 1, the number of wait states inserted by the memory controller is doubled from
OR
10.4.2.3.2
Figure 10-32
LCSn is connected directly to CE of the memory device. The LWE[0:1] signals are connected to the
respective WE[1:0] signals on the memory device where each LWE[0:1] signal corresponds to a different
data byte.
As
transaction are supplied by LOE or LWE
case shown in the figure). OR
strobe negation in write cycles. When this attribute is asserted, the strobe is negated one quarter of a clock
before the normal case provided that LCRR[CLDIV] = 4 or 8. For example, when ACS = 00 and
10-50
Figure 10-36
n
•
[SCY] cycles to 2×OR
Three clock cycles later (for LCRR[CLKDIV] = 2, 4, or 8), when OR
OR
n
[TRLX] = 1.
shows a basic connection between the local bus and a static memory device. In this case,
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
LWE n
LCLK
LCS n
LALE
Programmable Wait State Configuration
Chip-Select and Write Enable Negation Timing
LAD
LOE
TA
shows, the timing for LCSn is the same as for the latched address. The strobes for the
A
n
(XACS = 0, ACS = 00, CSNT = 1, SCY = 1, TRLX = 0, CLKDIV = 4, 8)
[SETA], wait states prolong the assertion duration of both LOE and LWE
Figure 10-33
Address
n
[SCY] cycles, allowing a maximum of 30 wait states.
n
n
[CSNT], along with ORn[TRLX], control the timing for the appropriate
[SETA] = 0. If LGTA is asserted externally two bus clock cycles or more
Figure 10-36. GPCM Basic Write Timing
shows two chip-select assertion timings for the case
n
, depending on the transaction direction—read or write (write
n
[SCY] and OR
Latched Address
Write Data
SCY = 1
n
[TRLX]. Internal generation of transfer
CSNT = 1
n
[XACS] = 1 and
Freescale Semiconductor
n
[ACS] = 10 or 11.
n
in the same