MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 15

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

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Number
10.3.1.22
10.3.1.23
10.4
10.4.1
10.4.1.1
10.4.1.2
10.4.1.3
10.4.1.4
10.4.1.5
10.4.1.6
10.4.2
10.4.2.1
10.4.2.2
10.4.2.3
10.4.2.3.1
10.4.2.3.2
10.4.2.3.3
10.4.2.3.4
10.4.2.3.5
10.4.2.4
10.4.2.5
10.4.3
10.4.3.1
10.4.3.1.1
10.4.3.1.2
10.4.3.1.3
10.4.3.2
10.4.3.2.1
10.4.3.2.2
10.4.3.2.3
10.4.3.2.4
10.4.3.2.5
10.4.3.3
10.4.3.3.1
10.4.3.3.2
10.4.3.3.3
10.4.3.3.4
10.4.3.3.5
10.4.3.4
10.4.3.4.1
10.4.3.4.2
Freescale Semiconductor
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Functional Description................................................................................................. 10-40
Basic Architecture.................................................................................................... 10-41
General-Purpose Chip-Select Machine (GPCM)..................................................... 10-45
Flash Control Machine (FCM) ................................................................................ 10-57
Flash Byte Count Register (FBCR) ..................................................................... 10-39
Flash ECC Blockn Register (FECC0–FECC3) ................................................... 10-39
Address and Address Space Checking ................................................................ 10-41
External Address Latch Enable Signal (LALE) .................................................. 10-41
Data Transfer Acknowledge (TA) ....................................................................... 10-43
Data Buffer Control (LBCTL)............................................................................. 10-44
Atomic Operation ................................................................................................ 10-44
Bus Monitor ......................................................................................................... 10-44
GPCM Read Signal Timing ................................................................................. 10-46
GPCM Write Signal Timing ................................................................................ 10-47
Chip-Select Assertion Timing ............................................................................. 10-49
External Access Termination (LGTA) ................................................................. 10-55
GPCM Boot Chip-Select Operation .................................................................... 10-56
FCM Buffer RAM ............................................................................................... 10-59
Programming FCM.............................................................................................. 10-62
FCM Signal Timing ............................................................................................. 10-65
FCM Boot Chip-Select Operation ....................................................................... 10-69
Programmable Wait State Configuration......................................................... 10-50
Chip-Select and Write Enable Negation Timing ............................................. 10-50
Relaxed Timing ............................................................................................... 10-51
Output Enable (LOE) Timing .......................................................................... 10-54
Extended Hold Time on Read Accesses .......................................................... 10-54
Buffer Layout and Page Mapping for Small-Page NAND Flash Devices ...... 10-59
Buffer Layout and Page Mapping for Large-Page NAND Flash Devices ...... 10-60
Error Correcting Codes and the Spare Region ................................................ 10-61
FCM Command Instructions ........................................................................... 10-63
FCM No-Operation Instruction ....................................................................... 10-64
FCM Address Instructions............................................................................... 10-64
FCM Data Read Instructions ........................................................................... 10-64
FCM Data Write Instructions .......................................................................... 10-65
FCM Chip-Select Timing ................................................................................ 10-65
FCM Command, Address, and Write Data Timing ......................................... 10-66
FCM Ready/Busy Timing................................................................................ 10-67
FCM Read Data Timing .................................................................................. 10-68
FCM Extended Read Hold Timing.................................................................. 10-69
FCM Bank 0 Reset Initialization ..................................................................... 10-70
Boot Block Loading into the FCM Buffer RAM............................................. 10-70
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