MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 382

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Integrated Programmable Interrupt Controller (IPIC)
Table 8-23
8.5.15
SERCR, shown in
either MCP_OUT or PCI_INTA in core-disable mode.
Table 8-24
8-24
Offset 0x44
Reset
Offset 0x48
Reset
0–31
0–30
Bits
Bits
31
W
W
R
R
0
0
Name
INT n Each implemented SERMR bit, listed in
defines the bit fields of SERMR.
defines the bit fields of SERCR.
System Error Control Register (SERCR)
MCPR
Name
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
—
The user masks an MCP by clearing and enables an interrupt by setting the corresponding SERMR bit.
When a masked MCP occurs, the corresponding SERSR bit is set, regardless of the setting of the SERMR
bit although no MCP request is passed to the core. The SERMR can be read by the user at any time.
Writes to unimplemented (reserved) bits are ignored; read = 0
Figure
Write ignored, read = 0
MCP route. Route MCP request to either MCP_OUT or PCI_INTA (in core disable mode).
0 MCP routed to PCI_INTA (in core disable mode).
1 MCP routed to MCP_OUT (in core disable mode).
Implemented bits reset to ones; unimplemented (reserved) bits reset to zeros.
8-18, defines the control bits that route MCP requests in core disable mode to
Figure 8-18. System Error Control Register (SERCR)
Figure 8-17. System Error Mask Register (SERMR)
Table 8-23. SERMR Field Descriptions
Table 8-24. SERCR Field Descriptions
INT
n (Implemented bits are listed in
Table
—
All zeros
8-21, corresponds to an external and an internal MCP source.
Description
Description
Table
8-21.)
Freescale Semiconductor
Access: Read/write
Access: Read/write
30
MCPR
31
31