MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 366

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Integrated Programmable Interrupt Controller (IPIC)
8-8
16–21
22–23
24–31
Bits
1–7
10
11
12
13
14
15
0
8
9
MPSB Mixed interrupts priority scheme for group B. Selects the relative MIXB priority scheme. It cannot be changed
MPSA Mixed interrupts priority scheme for group A. Selects the relative MIXA priority scheme. It cannot be changed
Name
IPSD Internal interrupts priority scheme for group D. Selects the relative SYSD priority scheme. It cannot be changed
IPSC Internal interrupts priority scheme for group C. Selects the relative SYSC priority scheme. It cannot be changed
IPSB Internal interrupts priority scheme for group B. Selects the relative SYSB priority scheme. It cannot be changed
IPSA Internal interrupts priority scheme for group A. Selects the relative SYSA priority scheme. It cannot be changed
HPIT HPI priority position IPIC output interrupt type. Defines which type of IPIC output interrupt signal ( int , cint , or
HPI
—
—
—
—
—
Write ignored, read = 0
Highest priority interrupt. Specifies the 7-bit unique interrupt number/vector (see
interrupt controller interrupt source that is advanced to the highest priority in the IPIC priority table (see
Table
Write ignored, read = 0
dynamically.
0 Grouped. The MIXBs are grouped by priority at the top of the table.
1 Spread. The MIXBs are spread by priority in the table.
dynamically.
0 Grouped. The MIXAs are grouped by priority at the top of the table.
1 Spread. The MIXAs are spread by priority in the table.
Write ignored, read = 0
dynamically.
0 Grouped. The SYSDs are grouped by priority at the top of the table.
1 Spread. The SYSDs are spread by priority in the table.
dynamically.
0 Grouped. The SYSCs are grouped by priority at the top of the table.
1 Spread. The SYSCs are spread by priority in the table.
dynamically.
0 Grouped. The SYSBs are grouped by priority at the top of the table.
1 Spread. The SYSBs are spread by priority in the table.
dynamically.
0 Grouped. The SYSAs are grouped by priority at the top of the table.
1 Spread. The SYSAs are spread by priority in the table.
Write ignored, read = 0
smi ) asserts its request to the core in the HPI priority position. These bits cannot be changed dynamically. (If
software really wants to change it, it has to make sure the corresponding interrupt source is masked or it won’t
happen during the change).
The definition of HPIT is as follows:
00 int request is asserted to the core for HPI.
01 smi request is asserted to the core for HPI.
10 cint request is asserted to the core for HPI.
11 Reserved.
Write ignored, read = 0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
8-31). HPI can be modified dynamically.
Table 8-4. SICFR Field Descriptions
Description
Table
Freescale Semiconductor
8-6) of the single