MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 421

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

9.4.1.13
The DDR SDRAM data initialization register, shown in
initialize memory if DDR_SDRAM_CFG2[D_INIT] is set.
Table 9-19
9.4.1.14
The DDR SDRAM clock control configuration register, shown in
adjustment.
Table 9-20
Freescale Semiconductor
Offset 0x130
Reset 0
0–31
9–31
Bits
Bits
0–4
5–7
8
W
Offset 0x128
Reset
R
W
0
R
Figure 9-15. DDR SDRAM Clock Control Configuration Register (DDR_SDRAM_CLK_CNTL)
INIT_VALUE Initialization value. Represents the value that DRAM is initialized with if DDR_SDRAM_CFG2[D_INIT]
CLK_ADJUST Clock adjust.
0
0
Figure 9-14. DDR SDRAM Data Initialization Configuration Register (DDR_DATA_INIT)
Name
describes the DDR_DATA_INIT fields.
describes the DDR_SDRAM_CLK_CNTL fields.
Name
—
—
—
—
0
DDR SDRAM Data Initialization (DDR_DATA_INIT)
DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
0
0
4
is set.
Reserved
000
001
010
011
100
101–111 Reserved
Reserved, should be cleared.
Reserved
CLK_ADJUST
0
5
Table 9-20. DDR_SDRAM_CLK_CNTL Field Descriptions
Clock is launched aligned with address/command
Clock is launched 1/4 applied cycle after address/command
Clock is launched 1/2 applied cycle after address/command
Clock is launched 3/4 applied cycle after address/command
Clock is launched 1 applied cycle after address/command
1
Table 9-19. DDR_DATA_INIT Field Descriptions
0
7
0
8
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
INIT_VALUE
All zeros
Figure
Description
Description
9-14, provides the value that is used to
Figure
—
9-15, provides a 1/4-cycle clock
Access: Read/Write
DDR Memory Controller
Access: Read/Write
31
9-27
31
0