MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 469

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
10–12
14–17
Bits
5–7
8–9
13
Name
G0CL General line 0 control. Determines which logical address line can be output to the LGPL0 pin when the UPM n
GPL4
RLF
AM
DS
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Address multiplex size. Determines how the address of the current memory cycle can be output on the
address pins. This field is needed when interfacing with devices requiring row and column addresses
multiplexed on the same pins. See
000 Internal transaction address a[8:23] driven on LA[10:25]; LAD[0:15] driven low.
001 Internal transaction address a[7:22] driven on LA[10:25]; LAD[0:15] driven low.
010 Internal transaction address a[6:21] driven on LA[10:25]; LAD[0:15] driven low.
011 Internal transaction address a[5:20] driven on LA[10:25]; LAD[0:15] driven low.
100 Internal transaction address a[4:19] driven on LA[10:25]; LAD[0:15] driven low.
101 Internal transaction address a[3:18] driven on LA[10:25]; LAD[0:15] driven low.
110 Reserved
111 Reserved
Disable timer period. Guarantees a minimum time between accesses to the same memory bank controlled
by UPM n . The disable timer is turned on by the TODT bit in the RAM array word, and when expired, the UPM n
allows the machine access to handle a memory pattern to the same bank. Accesses to a different bank by
the same UPM n is also allowed. To avoid conflicts between successive accesses to different banks, the
minimum pattern in the RAM array for a request serviced, should not be shorter than the period established
by DS.
00 1-bus clock cycle disable period
01 2-bus clock cycle disable period
10 3-bus clock cycle disable period
11 4-bus clock cycle disable period
is selected to control the memory access.
000 A12
001 A11
010 A10
011 A9
100 A8
101 A7
110 A6
111 A5
LGPL4 output line disable. Determines how the LGPL4/LUPWAIT pin is controlled by the corresponding bits
in the UPM n array. See
Read loop field. Determines the number of times a loop defined in the UPM n will be executed for a burst- or
single-beat read pattern or when M x MR[OP] = 11 (
0000 16
0001 1
0010 2
0011 3
...
1110 14
1111 15
Value
0
1
Table 10-11. M
LGPL4/LUPWAIT
LUPWAIT (input)
LGPL4 (output)
Pin Function
Table 10-40 on page
x
MR Field Descriptions (continued)
Section 10.4.4.4.7, “Address Multiplexing
Interpretation of UPM Word Bits
G4T1/DLT3
10-79.
Description
G4T1
DLT3
RUN
command)
G4T3/WAEN
WAEN
G4T3
(AMX)” for more information.
Enhanced Local Bus Controller
10-21