MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 468

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
10.3.1.4
The UPM machine mode registers (MAMR, MBMR and MCMR), shown in
configuration for the three UPMs.
Offset MAMR: 0x0_5070
Table 10-11
10-20
Reset
Reset
Bits
2–3
W
W
0
1
4
R
R
MBMR: 0x0_5074
MCMR: 0x0_5078
—
16
0
UWPL LUPWAIT polarity active low. Sets the polarity of the LUPWAIT pin when in UPM mode.
Name
RFEN Refresh enable. Indicates that the UPM needs refresh services. This bit must be set for UPMA (refresh
RLF
OP
—
RFEN
describes UPM mode fields.
UPM Mode Registers (M
17
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
1
Reserved
executor) if refresh services are required on any UPM assigned chip selects. If MAMR[RFEN] = 0, no refresh
services can be provided, even if UPMB and/or UPMC have their RFEN bit set.
0 Refresh services are not required
1 Refresh services are required
Command opcode. Determines the command executed by the UPM n when a memory access hits a UPM
assigned bank.
00 Normal operation
01 Write to UPM array. On the next memory access that hits a UPM assigned bank, write the contents of the
10 Read from UPM array. On the next memory access that hits a UPM assigned bank, read the contents of
11 Run pattern. On the next memory access that hits a UPM assigned bank, run the pattern written in the
0 LUPWAIT is active high.
1 LUPWAIT is active low.
MDR into the RAM location pointed to by MAD. After the access, MAD is automatically incremented.
the RAM location pointed to by MAD into the MDR. After the access, MAD is automatically incremented.
RAM array. The pattern run starts at the location pointed to by MAD and continues until the LAST bit is
set in the RAM word.
18
2
OP
3
WLF
UWPL
Figure 10-7. UPM Mode Registers (M
4
Table 10-11. M
21
5
AM
x
22
MR)
x
MR Field Descriptions
7
All zeros
All zeros
TLF
Description
8
DS
25
9
10
26
x
MR)
G0CL
Figure
12
Freescale Semiconductor
MAD
10-7, contain the
GPL4
13
Access: Read/Write
14
RLF
15
31