MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 641

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

In all cases of parity errors on the PCI bus, regardless of the parity-error-response bit, information about
the transaction is logged in the PCI error control capture register, the PCI error address capture register and
the PCI error data capture register; MCP is also asserted to the core as an option.
13.4.6
For inbound transactions (transactions generated by an external master on the PCI bus where the PCI
controller responds as a slave device), the PCI controller only responds to PCI addresses within the
windows mapped by the PCI inbound base address registers (PIBARs). If there is an address hit in one of
the PIBARs, the PCI address is translated from PCI space to local memory space through the associated
PCI inbound translation address registers (PITARs). This allows an external master to access local
memory. Each PIBAR register is associated with a PITAR and PIWAR which are located in the PCI
controller’s PCI CSR space.
accesses.
There are three full sets of inbound translation registers, in addition to the PIMMR base address register,
allowing four simultaneous translation windows, one to a fixed destination and three programmable. Only
two of the programmable windows can be mapped anywhere in the 64-bit PCI address space. Window 0
can only be mapped within the lowest 4-Gbyte space. Software can move the programmable translation
base addresses during run-time to access different portions of local memory, but the PCI inbound
translation windows may not overlap.
The translation windows are disabled after reset, that is, after reset, the PCI controller does not
acknowledge externally mastered transactions on the PCI bus by asserting PCI_DEVSEL until the
inbound translation windows are enabled.
Freescale Semiconductor
Window Size
PCI Inbound
PCI Inbound
Address
PCI Inbound Address Translation
Base
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
4G
0
PCI Memory View
System memory
Figure 13-54. Inbound PCI Memory Address Translation
PCI Memory
Peripheral
Memory
Figure 13-54
shows an example translation window for inbound memory
Inbound Address
Translation
4G
0
Peripheral Memory
Local Bus View
Local Memory
PCI Memory
Window
PCI Inbound
Translation
Address
PCI Inbound
Window Size
PCI Bus Interface
13-59