MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 508

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
512 bytes appear as main region data, and 16 bytes appear as spare region data. The EEPROM’s page
numbered P is associated with buffer number (P mod 8), where P = FPAR[PI]. Since the bank size set by
ORn[AM] will be greater than 8 Kbytes, an identical image of the FCM buffer RAM appears replicated
every 8 Kbytes throughout the bank address space. It is recommended that the bank size be set to 32
Kbytes, which covers a single NAND Flash block for small-page devices.
For FCM commands, register FPAR sets the page address and, therefore, also the buffer number.In the case
that FBCR[BC] = 0, FCM transfers an entire page, comprising the 512-byte main region followed by the
16-byte spare region; the 496-byte reserved region is not accessed, and remains undefined for software.
However, for commands given a specific byte count in FBCR[BC], FPAR[MS] locates the starting address
in either the main region (MS = 0) or the spare region (MS = 1). Where different eLBC banks control both
small and large-page devices, a large-page 4-Kbyte buffer must be assigned to either the first 4 or last 4
small-page buffers.
10.4.3.1.2
The FCM buffer space is divided into two 4 Kbyte buffers for large-page devices (ORn[PGS] = 1), mapped
as shown in
appear as main region data, and 64 bytes appear as spare region data. The EEPROM’s page numbered P
is associated with buffer number (P mod 2), where P = FPAR[PI]. Since the bank size set by ORn[AM]
will be greater than 8 Kbytes, an identical image of the FCM buffer RAM appears replicated every 8
Kbytes throughout the bank address space. It is recommended that the bank size be set to 256 Kbytes,
which covers a single NAND Flash block for large-page devices.
For FCM commands, register FPAR sets the page address and, therefore, also the buffer number. In the
case that FBCR[BC] = 0, FCM transfers an entire page, comprising the 2048-byte main region followed
by the 64-byte spare region; the 1984-byte reserved region is not accessed, and remains undefined for
10-60
Bank Base Address
Figure 10-46. FCM Buffer RAM Memory Map for Small-Page (512-byte page) NAND Flash Devices
offset 0x0C00
offset 0x1C00
offset 0x0400
offset 0x0800
offset 0x1000
offset 0x1400
offset 0x1800
offset 0x2000
End of Bank
Figure
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Buffer Layout and Page Mapping for Large-Page NAND Flash Devices
10-47. Each page in a large-page NAND Flash comprises 2112 bytes, where 2048 bytes
buffer #0/page 0
buffer #1/page 1
buffer #2/page 2
buffer #3/page 3
buffer #4/page 4
buffer #5/page 5
buffer #6/page 6
buffer #7/page 7
replicated FCM
buffer RAM
images in bank
1 Kbyte page buffer:
512-byte main region (FPAR[MS] = 0)
16-byte spare region (FPAR[MS] = 1)
496-byte reserved region (FPAR[MS] = 1)
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