MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 113

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
0x0_0A0C–
0x0_0924–
0x0_09FC
0x0_0AFC
0x0_090C
0x0_091C
0x0_0A00
0x0_0A04
0x0_0A08
0x00B14–
0x0_0908
0x0_0910
0x0_0914
0x0_0918
0x0_0920
0x00B0C
0x00BFC
0x00B00
0x00B04
0x00B08
0x00B10
0xC0C
0xC00
0xC04
0xC08
0xC10
0xC14
0x000
0x008
0x080
Offset
Reserved, should be cleared
Reserved, should be cleared
Reset status register (RSR)
Reset mode register (RMR)
Reset protection register (RPR)
Reset control register (RCR)
Reset control enable register (RCER)
Reserved, should be cleared.
System PLL mode register (SPMR)
Output clock control register (OCCR)
System clock control register (SCCR)
Reserved, should be cleared
Power management controller configuration register
(PMCCR)
Power management controller event register (PMCER)
Power management controller mask register (PMCMR)
Power management controller configuration register 1
(PMCCR1)
Power management controller configuration register 2
(PMCCR2)
Reserved
GPIO direction register (GPDIR)
GPIO open drain register (GPODR)
GPIO data register (GPDAT)
GPIO interrupt event register (GPIER)
GPIO interrupt mask register (GPIMR)
GPIO external interrupt control register (GPICR)
CS0_BNDS—Chip select 0 memory bounds
CS1_BNDS—Chip select 1 memory bounds
CS0_CONFIG—Chip select 0 configuration
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Register
Table 2-2. Memory Map (continued)
DDR Memory Controller Memory Map
Power Management Control Module
GPIO Registers
Clock Module
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
—
—
—
—
—
R
0x7DDF_FFFF
0x0000_80C0
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x nnnn _ nnnn
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0002_0002
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Undefined
Reset
—
—
—
—
—
Section/Page
4.5.1.3/4-33
4.5.1.4/4-35
4.5.1.5/4-35
4.5.1.6/4-36
4.5.1.7/4-37
4.5.2.1/4-37
4.5.2.2/4-39
4.5.2.3/4-40
5.8.2.1/5-67
5.8.2.2/5-68
5.8.2.3/5-70
5.8.2.4/5-70
5.8.2.5/5-72
9.4.1.2/9-10
21.3.1/21-3
21.3.3/21-4
21.3.4/21-4
21.3.5/21-4
21.3.6/21-5
9.4.1.1/9-9
9.4.1.1/9-9
8.6/8-28
—
—
—
—
—
Memory Map
2-9