MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 264

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

System Configuration
The GTCFR2 register is shown in
5-56
Offset
Bits
4
5
6
7
Reset
W
R
0x04
Name
RST1
STP1
GM2
GM1
PCAS
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
0
Gate mode for TGATE2
0 Restart gate mode. The TGATE2 pin is used to enable/disable count. A low level of TGATE2 enables and
1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE2 does not restart the
Gate mode for TGATE1
0 Restart gate mode. The TGATE1 is used to enable/disable count. A low level of TGATE1 enables and a
1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE1 does not restart the
Note: In backward compatible mode (GTCFR1[BCM] = 0) this bit is ignored. GTCFR1[GM2] bit will control
Stop timer 1
0 Normal operation
1 Reduce power consumption of the corresponding timer. This bit stops all clocks to the timer 1, except the
Reset timer 1
0 Reset the timer 1, including GTMDR1, GTRFR1, GTCNR1, GTCPR1, and GTEVR1 (a software reset is
1 Enable the corresponding timer if the STP1 bit is cleared.
a falling edge of TGATE2 restarts the count (reset the dynamic counter’s count value to 0) and a high
level of TGATE2 disables the count.
appropriate count value in GTCNR2[CNV2].
falling edge of TGATE1 restarts the count (reset the dynamic counter’s count value to 0) and a high level
of TGATE1 disables the count.
appropriate count value in GTCNR1[CNV1].
register interface clock, which allows to read and write timer registers. The clocks to the timer remain
stopped until the user clears this bit or a hardware reset occurs.
identical to an external reset).
Figure 5-41. Global Timers Configuration Register 2 (GTCFR2)
the gate mode for timers 1 and 2.
SCAS
1
Table 5-57. GTCFR1 Bit Settings (continued)
Figure
STP4
2
5-41.
RST4
3
All zeros
Description
GM4
4
GM3
5
Freescale Semiconductor
STP3
6
Access: Read/Write
RST3
7