MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 668

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Security Engine (SEC) 2.2
Table 14-16
14-26
0–49
Bits
50
51
52
53
54
55
56
57
58
Reset
Field
Addr
R/W
Name
KPE
ERE
KSE
DSE
OFE
ME
AE
CE
—
IE
describes DEUICR fields.
0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved
Key parity error. The defined parity bits in the keys written to the key registers did not reflect odd parity
correctly. (Note that key register 2 and key register 3 are only checked for parity if the appropriate DEU mode
register bit indicates triple DES.
0 Key parity error enabled
1 Key parity error disabled
Internal error. An internal processing error was detected while performing encryption.
0 Internal error enabled
1 Internal error disabled
Early read error. The DEU IV register was read while the DEU was performing encryption.
0 Early read error enabled
1 Early read error disabled
Context error. A DEU key register, the key size register, the data size register, the mode register, or IV register
was modified while DEU was performing encryption.
0 Context error enabled
1 Context error disabled
Key size error. An inappropriate value (8 being appropriate for single DES, and 16 and 24 being appropriate
for Triple DES) was written to the DEU key size register
0 Key size error enabled
1 Key size error disabled
Data size error (DSE): A value that is not a multiple of 64 bits was written to the DEU data size register.
0 Data size error enabled
1 Data size error disabled
Mode error. An illegal value was detected in the mode register.
0 Mode error enabled
1 Mode error disabled
Address error. An illegal read or write address was detected within the DEU address space.
0 Address error enabled
1 Address error disabled
Output FIFO error. The shared symmetric output FIFO was detected non-empty upon write of DEU data size
register
0 Output FIFO non-empty error enabled
1 Output FIFO non-empty error disabled
—
Figure 14-13. DEU Interrupt Control Register (DEUICR)
49
KPE
Table 14-16. DEUICR Field Descriptions
50
51
IE
ERE CE KSE DSE ME
52
53
DEU 0x3_2038
54
3000
R/W
Description
55
56
AE OFE IFE IFU IFO OFU OFO
57
58
59
60
Freescale Semiconductor
61
62
63