MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 671

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 14-17
Freescale Semiconductor
The following bits are described for information only. They are not under direct user control.
The following bits are controlled through the MODE0 or MODE1 fields of the descriptor header.
0–53
Bits
54
55
56
57
58
59
60
Reset
Field
Addr
R/W
NEW=0 Determines the configuration of the MDEU mode register (MDEUMR). This table shows the configuration
CONT
SMAC
HMAC
Name
CICV
INIT
0
—
—
describes MDEUMR fields in ‘old’ configuration.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved
for NEW = 0.
Reserved, must be set to zero
Continue. Most operations will require this bit to be cleared. It is set only when the data to be hashed is
spread across multiple descriptors.
The value programmed in PD must be opposite to the value in this bit.
0 Do autopadding and complete the message digest. Used when the entire hash is performed with one
1 This hash will be continued in a subsequent descriptor. Do not autopad and do not complete the
Compare integrity check values
0 Normal operation; no ICV comparison
1 After the message digest (ICV) is computed, compare it to the data in the MDEU’s input FIFO. If the ICVs
Only applicable to descriptor types that provide for reading an ICV in value.
Specifies whether to perform an SSL-MAC operation
0 Normal operation
1 Perform an SSL3.0 MAC operation. This requires a key and key length. If this is set then the HMAC bit
Initialization bit. Most operations will require this bit to be set. Cleared only for operations that load context
from a known intermediate hash value.
0 Do not initialize digest registers. In this case the registers must be loaded from a hash context pointer in
1 Do an algorithm-specific initialization of the digest registers.
Specifies whether to perform an HMAC operation
0 Normal operation
1 Perform an HMAC operation. This requires a key and key length. If this is set then the SMAC bit should
Figure 14-15. MDEU Mode Register (MDEUMR) in ‘Old’ Configuration
descriptor, or on the last of a sequence of descriptors.
message digest.
do not match, send an error interrupt to the channel. The number of bytes to be compared is given by
the ICV size register.
should be 0.
the descriptor. When the data to be hashed is spread across multiple descriptors, this bit must be 0 on
all but the first descriptor.
be 0.
—
Table 14-17. MDEUMR in ‘Old’ Configuration
53
NEW=0
MDEU 0x3_6000
54
R/W
0
—
55
Description
CONT CICV SMAC INIT HMAC PD
56
57
58
59
60
Security Engine (SEC) 2.2
61
62
ALG
63
14-29