MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 611

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Offset 06
13.3.3.4
This register is used to record status information for PCI bus-related events. Some of the bits are
hard-wired to indicate the capabilities of the PCI controller. Other bits can be cleared by writing 1 to the
bit location.
Table 13-26
Freescale Semiconductor
Reset
W
R DPERR SSERR RMA
10–9
Bits
2–0
15
14
13
12
11
8
7
6
5
4
3
w1c
15
0
Figure 13-22
DEVSEL_T DEVSEL timing. Hard-wired to 00.
shows the bit settings of the PCI status register.
PCI Status Configuration Register
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
DPERR
SSERR
FB-BC
Name
RMA
INTS
DPD
66M
RTA
STA
w1c
CL
—
—
14
0
Table 13-26. PCI Status Configuration Register Field Descriptions
w1c
13
Detected parity error. Set whenever the PCI controller detects a parity error on the PCI bus, even
if parity error handling is disabled (as controlled by bit 6 in the PCI Command register).
Signaled system error. Set whenever PCI_SERR is asserted.
Received master abort. Set whenever the PCI controller, acting as the PCI master on the PCI bus,
terminates a transaction (except for a special-cycle) using master-abort.
Received target abort. Set whenever a transaction initiated by this PCI controller on the PCI bus is
terminated by a target-abort.
Signaled target abort. Set whenever the PCI controller, acting as the PCI target on the PCI bus,
issues a target-abort to a PCI master.
Master data parity error. Set when a data parity error is detected on the PCI bus, if the PCI controller
is the master that initiated the transaction and bit 6 in the PCI command register is set.
Fast back-to-back capable. Hard-wired to 1.
Reserved
66-MHz capable. Hard-wired to 1.
Capabilities list. Hard-wired to 1.
Interrupt status. Contains the status of the device interrupt. The value of this bit is not affected by
the INTD bit of the PCI command configuration register.
Reserved
0
shows the PCI status fields.
RTA
w1c
Figure 13-22. PCI Status Configuration Register
12
0
STA
w1c
11
0
DEVSEL_T
10
0
9
0
DPD FB-BC
w1c
0
8
Description
1
7
—
0
6
66M
1
5
CL
1
4
INTS
w1c
0
3
PCI Bus Interface
0
2
Access: Mixed
—
0
13-29
0
0