MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1086

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

I
includes collision detection and arbitration that prevent data corruption if two or more masters attempt to
control the bus simultaneously.
17.1.1
Each I
17.1.2
The I
17-2
2
C Interfaces
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2
C unit on this device can operate in one of the following modes:
2
C interface includes the following features:
Two-wire interface
Multiple-master operational
Arbitration lost interrupt with automatic mode switching from master to slave
Calling address identification interrupt
START and STOP signal generation/detection
Acknowledge bit generation/detection
Bus busy detection
Software-programmable clock frequency
Software-selectable acknowledge bit
On-chip filtering for spikes on the bus
Master mode. The I
cannot use its own slave address as a calling address. The I
simultaneously.
Slave mode. The I
condition from an I
Interrupt-driven byte-to-byte data transfer. When successful slave addressing is achieved (and
SCLn returns to zero), the data transfer can proceed on a byte-to-byte basis in the direction
specified by the R/W bit sent by the calling master. Each byte of data must be followed by an
acknowledge bit, which is signaled from the receiving device. Several bytes can be transferred
during a data transfer session.
Boot sequencer mode. I
initialize the configuration registers in the device after the I
sequencer mode is selected using the BOOTSEQ field in the reset configuration word high. Note
that the hard-coded reset configuration word high value is boot sequencer mode disabled. This
mode is not supported by I
Reset configuration load (I
words from an EEPROM at a specific calling address while the rest of the device is in the reset
state (HRESET asserted). Once the reset configuration words are latched inside the device, I
reset until HRESET is negated. After HRESET is negated, the device may be initialized using boot
sequence mode according to the BOOTSEQ field in the reset configuration word. See
Section 17.4.5, “Boot Sequencer Mode.”
Features
Modes of Operation
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
2
C is addressed by an I
2
2
C master is detected.
C initiates a transfer, generates clock signals, and terminates a transfer. It
2
C1 controller supports boot sequencer mode. This mode can be used to
2
2
C1 only). In this mode, the I
C2 controller.
2
C master. The module must be enabled before a START
2
C1 interface loads the reset configuration
2
2
C cannot be a master and a slave
C module is initialized. Boot
Freescale Semiconductor
2
C1 is