MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1117

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 18-9
18.3.1.5
The UIIRs indicate when an interrupt is pending from the corresponding UART and what type of interrupt
is active. They also indicate if the FIFOs are enabled.
The DUART prioritizes interrupts into four levels and records these in the corresponding UIIR. The four
levels of interrupt conditions in order of priority are as follows:
See
When the UIIR is read, the associated DUART serial channel freezes all interrupts and indicates the
highest priority pending interrupt. While this read transaction is occurring, the associated DUART serial
channel records new interrupts, but does not change the contents of UIIR until the read access is complete.
Figure 18-7
Freescale Semiconductor
Bits
0–3
4
5
6
7
1. Receiver line status
2. Received data ready/character time-out
3. Transmitter holding register empty
4. MODEM status
Table 18-11
ETHREI Enable transmitter holding register empty interrupt
ERDAI
ERLSI
Name
EMSI
Offset: 0x0_4502, 0x0_4602
Reset
—
describes the UIER fields.
shows the bits in the UIIR.
Interrupt ID Registers (UIIR1 and UIIR2)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
W
R
for more details.
Reserved
Enable MODEM status interrupt
0 Mask interrupts caused by UMSR[DCTS] being set.
1 Enable and assert interrupts when UMSR[CTS] changes state.
Enable receiver line status interrupt
0 Mask interrupts when ULSR’s overrun, parity error, framing error, or break interrupt bits are set.
1 Enable and assert interrupts when ULSR’s overrun, parity error, framing error or break interrupt bits are
0 Mask interrupt when ULSR[THRE] is set.
1 Enable and assert interrupts when ULSR[THRE] is set.
Enable received data available interrupt
0 Mask interrupt when new receive data is available or receive data time-out has occurred.
1 Enable and assert interrupts when a new data character is received from the external device and/or a
set.
time-out interrupt occurs in FIFO mode.
0
0
FE
Figure 18-7. Interrupt ID Registers (UIIR1 and UIIR2)
0
1
Table 18-9. UIER Field Descriptions
0
2
—
3
0
Description
IID3
0
4
IID2
0
5
Access: User read-only
IID1
0
6
IID0
1
7
DUART
18-9