MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 565

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

12.3.3
The inbound message registers can be read from the PCI bus and the CSB in both host and agent modes.
They can be written only from the PCI bus.
Table 12-4
12.3.4
The outbound message registers can be read from the PCI bus and the CSB in both host and agent modes.
They can be written only from the CSB.
Table 12-5
Freescale Semiconductor
Offset 0x050, 0x054
Offset 0x058, 0x05C
Reset
Reset
31–0
31–0
Bits
Bits
Bits
1
0
W
W
R
R
31
31
OM1IM Outbound message 1 interrupt mask.
OM0IM Outbound message 0 interrupt mask.
IMSG n Inbound message n. Contains generic data to be passed between the local processor and external hosts.
OMSG n Outbound message n . Contains generic data to be passed between the local processor and external hosts.
Name
Name
Name
describes the IMRn register.
describes the OMRn registers.
Inbound Message Registers (IMR0–IMR1)
Outbound Message Registers (OMR0–OMR1)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
0 Outbound message 1 interrupt is allowed
1 Outbound message 1 interrupt is masked
0 Outbound message 0 interrupt is allowed
1 Outbound message 0 interrupt is masked
Figure 12-5. Outbound Message Registers (OMR0–OMR1)
Figure 12-4. Inbound Message Registers (IMR0, IMR1)
Table 12-3. OMIMR Field Descriptions (continued)
Table 12-5. OMR0 and OMR1 Field Descriptions
Table 12-4. IMR0 and IMR1 Field Descriptions
Figure 12-4
All zeros
All zeros
OMSG n
IMSG n
Description
Description
Description
shows the IMR0 and IMR1 fields.
Access: User Read/Write
Access: User Read/Write
DMA/Messaging Unit
12-5
0
0