MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 6

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Paragraph
Number
5.2.1
5.2.2
5.2.3
5.2.3.1
5.2.4
5.2.4.1
5.2.4.1.1
5.2.4.2
5.2.4.3
5.2.4.3.1
5.2.4.4
5.2.4.4.1
5.2.4.5
5.2.4.5.1
5.2.4.6
5.2.4.6.1
5.2.4.7
5.2.4.7.1
5.2.4.8
5.2.4.8.1
5.2.5
5.2.6
5.2.7
5.2.8
5.2.9
5.2.9.1
5.2.10
5.2.11
5.3
5.3.1
5.3.2
5.3.2.1
5.3.2.2
5.3.2.3
5.3.2.3.1
vi
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
System Configuration .................................................................................................... 5-16
Address Translation and Mapping ............................................................................... 5-3
Window into Configuration Space............................................................................... 5-4
Local Access Windows................................................................................................ 5-4
Local Access Register Descriptions ............................................................................ 5-6
Precedence of Local Access Windows ...................................................................... 5-14
Configuring Local Access Windows ......................................................................... 5-14
Distinguishing Local Access Windows from Other Mapping Functions .................. 5-14
Outbound Address Translation and Mapping Windows............................................ 5-15
Inbound Address Translation and Mapping Windows .............................................. 5-15
Internal Memory Map................................................................................................ 5-15
Accessing Internal Memory from External Masters.................................................. 5-16
System Configuration Register Memory Map........................................................... 5-16
System Configuration Registers ................................................................................ 5-17
Local Access Register Memory Map ...................................................................... 5-4
Internal Memory Map Registers Base Address Register (IMMRBAR).................. 5-6
Alternate Configuration Base Address Register (ALTCBAR)................................ 5-7
LBC Local Access Window n Base Address Registers
LBC Local Access Window n Attributes Registers (LBLAWAR0–
PCI Local Access Window n Base Address Register
PCI Local Access Window n Attributes Registers
DDR Local Access Window n Base Address Registers
DDR Local Access Window n Attributes Registers (DDRLAWAR0–
PCI Inbound Windows........................................................................................... 5-15
System General Purpose Register Low (SGPRL) ................................................. 5-17
System General Purpose Register High (SGPRH) ................................................ 5-17
System Part and Revision ID Register (SPRIDR) ................................................. 5-18
Updating IMMRBAR .......................................................................................... 5-6
(LBLAWBAR0–LBLAWBAR3) ........................................................................ 5-8
LBLAWBAR0[BASE_ADDR] Reset Value ....................................................... 5-8
LBLAWAR3) ....................................................................................................... 5-9
LBLAWAR0[EN] and LBLAWAR0[SIZE] Reset Value .................................... 5-9
(PCILAWBAR0–PCILAWBAR1) .................................................................... 5-10
PCILAWBAR0[BASE_ADDR] Reset Value.................................................... 5-10
(PCILAWAR0–PCILAWAR1) .......................................................................... 5-11
PCILAWAR0[EN] and PCILAWAR0[SIZE] Reset Value ................................ 5-11
(DDRLAWBAR0–DDRLAWBAR1)................................................................ 5-12
DDRLAWBAR0[BASE_ADDR] Reset Value.................................................. 5-12
DDRLAWAR1).................................................................................................. 5-13
DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset Value............................ 5-13
SPRIDR[PARTID] Coding ................................................................................ 5-18
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