MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1211

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Index
Freescale Semiconductor
GPIO, 21-2
groupings figure, 3-3
I
IPIC, 8-5–8-6
JTAG interface, 20-1–20-3
LBC
muxing, 3-14
output, states during reset, 3-13
overview, 3-1, 7-37
2
C
EC_MDC (eTSEC management data clock), 15-9
EC_MDIO (eTSEC management data input/output,
TSECn_COL (eTSEC 1–4 collision input), 15-8
TSECn_CRS (eTSEC 1–4 carrier sense input/FIFO
TSECn_GTX_CLK (eTSEC 1–4 gigabit transmit clock),
TSECn_RX_CLK (eTSEC 1–4 receive clock), 15-9
TSECn_RX_DV (eTSEC 1–4 receive data valid), 15-9
TSECn_RX_ER (eTSEC 1–4 receive error), 15-10
TSECn_RXD[7:0] (eTSEC 1–4 receive data in), 15-9
TSECn_TX_CLK (eTSEC 1–4 transmit clock in), 15-10
TSECn_TX_EN (eTSEC 1–4 transmit data valid), 15-10
TSECn_TX_ER (eTSEC 1–4 transmit error), 15-10
TSECn_TXD[7:0] (eTSEC 1–4 transmit data out), 15-10
SCL (serial clock), 17-3, 17-4
SDA (serial data), 17-3, 17-4
cint (critical interrupt), 8-2
int (internal interrupt), 8-2
mcp (machine check processor), 8-2
smi (system management interrupt), 8-2
LA[27:31] (non-multiplexed address), 10-6
LAD[0:31] (multiplexed address/data), 10-7
LALE (external address latch enable), 10-5, 10-41
LBCTL (data buffer control), 10-6, 10-44
LBS[0:3] (UPM byte select), 10-5
LCK[0:2] (clock), 10-7
LCS[0:7] (chip select), 10-5
LCS0 (LBC chip select 0), 10-56, 10-69
LGPL0 (GP line 0), 10-6
LGPL1 (GP line 1), 10-6
LGPL2 (GP line 2), 10-6
LGPL3 (GP line 3), 10-6
LGPL4 (GP line 4), 10-6
LGPL5 (GP line 5), 10-6
LGTA (GPCM transfer acknowledge), 10-6, 10-55
LOE (GPCM output enable), 10-6
LWE[0:3] (GPCM write enable), 10-5
MDVAL (debug mode data valid), 10-7
MSRCID[0:4] (debug source ID), 10-7
TA (data transfer acknowledge), 10-43
UPWAIT (UPM wait), 10-6, 10-73
BIDI), 15-9
receiver flow control), 15-8
15-8
MPC8313E PowerQUICC™ II Pro Integrated Processor Reference Manual, Rev. 2
Single-step
smi (system management interrupt signal), 8-2
Snapshot arbiters, 14-65
Software watchdog timer, see Watchdog timer (WDT)
SPI, 1-18
Split transaction isochronous transfer descriptor (siTD), see
Split transactions, see USB interface, split transactions
SPRG0–SPRG7, 7-3
SPRs (special purpose registers), 7-16–7-20
SRESET, 4-9
SRn (segment registers 0–15), 7-19
Supervisor-level SPRs, 7-19
SYS_CLK_IN signal, 4-3
System call (sc), 7-33
System configuration
System interface, 16-45
PCI, 13-4–13-11
reset, 4-1–4-2
reset and clocking blocks, 5-51
USB interface, 16-3–16-5
trace enable (SE), 7-18
block diagram, 19-2
features, 19-2
initialization/application information, 19-16
memory map/register definition, 19-8
modes of operation, 19-3
registers, 19-9–19-16
signals, 19-6–19-8
transmission and reception process, 19-3
local memory map overview, 5-1
overview, 5-1
registers, 5-17
INTA, 12-15
PCI_C/BE[7:0] (command/byte enable), 13-6
PCI_PERR (parity error), 13-9
PCI_PME (PME signal), 13-9
PCI_REQ[4:0] (bus request), 13-9
PCI_SERR (system error), 13-10
PCI_STOP (stop), 13-10
PCI_TRDY (target ready), 13-11
configuration, 4-9
see also USB interface, signals
master programming example, 19-16
slave programming example, 19-16
master, 19-3
multiple-master, 19-5
slave, 19-4
by acronym, see Register Index
descriptions, 19-7
overview, 19-7
USB interface, split transaction isochronous transfer
descriptor (siTD)
Index-13
S–S